ISP1583ETUM STEricsson, ISP1583ETUM Datasheet - Page 65
ISP1583ETUM
Manufacturer Part Number
ISP1583ETUM
Description
Manufacturer
STEricsson
Datasheet
1.ISP1583ETUM.pdf
(100 pages)
Specifications of ISP1583ETUM
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NXP Semiconductors
Table 92.
ISP1583_7
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Test Mode register: bit allocation
unchanged
FORCEHS
R/W
7
0
Table 93.
Bit
7
6 to 5
4
3
2
1
0
Symbol
FORCEHS
-
FORCEFS
PRBS
KSTATE
JSTATE
SE0_NAK
6
-
-
-
Test Mode register: bit description
reserved
Rev. 07 — 22 September 2008
Description
Force High-Speed: Logic 1 forces the hardware to high-speed mode only
and disables the chirp detection logic.
reserved
Force Full-Speed: Logic 1 forces the physical layer to full-speed mode only
and disables the chirp detection logic.
Predetermined Random Pattern: Logic 1 sets the DP and DM pins to
toggle in a predetermined random pattern.
K-State: Logic 1 sets the DP and DM pins to the K state.
J-State: Logic 1 sets the DP and DM pins to the J state.
SE0 NAK: Logic 1 sets the DP and DM pins to a high-speed quiescent
state. The device only responds to a valid high-speed IN token with a NAK.
5
-
-
-
unchanged
FORCEFS
R/W
4
0
PRBS
R/W
3
0
0
Hi-Speed USB peripheral controller
KSTATE
R/W
2
0
0
JSTATE
R/W
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1583
SE0_NAK
R/W
0
0
0
64 of 99
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