FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 160
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FW82801DB S L66K
Manufacturer Part Number
FW82801DB S L66K
Description
Manufacturer
Intel
Datasheet
1.FW82801DB_S_L66K.pdf
(587 pages)
Specifications of FW82801DB S L66K
Lead Free Status / RoHS Status
Supplier Unconfirmed
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Functional Description
160
Table 5-51. GPIO Implementation (Sheet 2 of 2)
NOTES:
1. All GPIOs default to their alternate function.
2. All inputs are sticky. The status bit remains set as long as the input was asserted for 2 clocks. GPIs are
3. GPIO[0:7] are 5 V tolerant, and all GPIs can be routed to cause an SCI or SMI#.
4. If GPIO_USE_SEL bit 1 is set to 1 and GEN_CNT bit 25 is also set to 1 then REQ/GNT[5]# is enabled. See
GPIO[27:28]
GPIO[29:31]
GPIO[32:43]
GPIO[25]
GPIO[26]
GPO[16]
GPO[17]
GPO[18]
GPO[19]
GPO[20]
GPO[21]
GPO[22]
GPIO[23
GPIO[24]
sampled on PCI clocks in S0/S1. GPIs are sampled on RTC clocks in S3/S4/S5 .
Section
GPIO
9.1.22.
Output
Output
Output
Output
Output
Output
Output
Output
Type
Only
Only
Only
Only
Only
Only
Only
Only
N/A
N/A
I/O
I/O
I/O
I/O
Function
GNT[B]# or
Alternate
Unmuxed
Unmuxed
Unmuxed
GNT[A]#
GNT[5]#
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(1)
Resume
Resume
Resume
Power
Core
Core
Core
Core
Core
Core
Core
Core
Core
Well
N/A
N/A
Tolerant
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
• Output controlled via GP_LVL register
• TTL driver output
• Output controlled via GP_LVL register
• TTL driver output
• Output controlled via GP_LVL register
• TTL driver output
• Output controlled via GP_LVL register
• TTL driver output
• Output controlled via GP_LVL register
• TTL driver output
• This GPO defaults high.
• Output controlled via GP_LVL register
• TTL driver output
• Output controlled via GP_LVL register
• Open-drain output
• Output controlled via GP_LVL register
• TTL driver output
• Input active status read from GP_LVL
• Output controlled via GP_LVL register
• TTL driver output
• Blink enabled via GPO_BLINK register
• Input active status read from GP_LVL
• Output controlled via GP_LVL register
• TTL driver output
• Not implemented
• Input active status read from GP_LVL
• Output controlled via GP_LVL register
• TTL driver output
• Not implemented
bit 16.
bit 17.
bits [18:19].
bits [18:19].
bit 20.
bit 21.
bit [22].
bit [23].
register bit 24.
bit 24.
bit 25.
register bit 25
bit 25.
register bits [27:28]
bits [27:28]
Intel
®
82801DB ICH4 Datasheet
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