W83627DHG-P Nuvoton Technology Corporation of America, W83627DHG-P Datasheet - Page 161

• Manufacturer Part Number: W83627DHG-P
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-P

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

12. UART PORT
12.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format for transmission and to convert serial
data into parallel format during reception. The serial data format is a start bit, followed by five to eight
data bits, a parity bit (if programmed) and one, one-and-a-half (five-bit format only) or two stop bits.
The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the
internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic.
The UARTs also support the MIDI data rate. Furthermore, the UARTs also include a complete modem
control capability and 16-byte FIFOs for reception and transmission to reduce the number of interrupts
presented to the CPU.
12.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register defines and controls the protocol for asynchronous data communication,
including data length, stop bit, parity, and baud rate selection.
12.2 Register Description
DEFAULT
BIT
NAME
7
6
5
4
3
2
BIT
BDLAB. Baudrate Divisor Latch Access Bit. When this bit is set to logical 1, designers
can access the divisor (in 16-bit binary format) from the divisor latches of the baud-rate
generator during a read or write operation. When this bit is set to logical 0, the Receiver
Buffer Register, the Transmitter Buffer Register, and the Interrupt Control Register can be
accessed.
SSE. Set Silence Enable. A logical 1 forces the Serial Output (SOUT) to a silent state (a
logical 0). Only IRTX is affected by this bit; the transmitter is not affected.
PBFE. Parity Bit Fixed Enable. When PBE and PBFE of UCR are both set to logical 1,
(1) If EPE is logical 1, the parity bit is fixed at logical 0 when transmitting and checking.
(2) If EPE is logical 0, the parity bit is fixed at logical 1 when transmitting and checking.
EPE. Even Parity Enable. When PBE is set to logical 1, this bit counts the number of
logical 1’s in the data word bits and determines the parity bit. When this bit is set to logical
1, the parity bit is set to logical 1 if an even number of logical 1’s are sent or checked.
When the bit is set to logical 0, the parity bit is logical 1 if an odd number of logic 1’s are
sent or checked.
PBE. Parity Bit Enable. When this bit is set to logical 1, the transmitter inserts a stop bit
between the last data bit and the stop bit of the SOUT, and the receiver checks the parity
bit in the same position.
MSBE. Multiple Stop Bits Enable. This bit defines the number of stop bits in each serial
character that is transmitted or received.
(1) If MSBE is set to logical 0, one stop bit is sent and checked.
(2) If MSBE is set to logical 1 and the data length is 5 bits, one-and-a-half stop bits are
(3) If MSBE is set to logical 1 and the data length is 6, 7 or 8 bits, two stop bits are sent
sent and checked.
BDLAB
7
0
SSE
6
0
PBFE
5
0
W83627DHG-P/W83627DHG-PT
DESCRIPTION
-151-
EPE
4
0
PBE
3
0
Publication Release Date: July 09, 2009
MSBE
2
0
DLS1
1
0
Version 1.94
DLS0
0
0