ISP1760BEGA STEricsson, ISP1760BEGA Datasheet - Page 81

• Manufacturer Part Number: ISP1760BEGA
• Manufacturer: STEricsson

Specifications of ISP1760BEGA

• Package Type: LQFP
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Table 82.
CD00222702
Product data sheet
Bit
7 to 0
DW3
63
62
61
60
59
58
57
56 to 55
54 to 44
43 to 32
DW2
31 to 24
23 to 8
7 to 0
DW1
63 to 57
56 to 50
49 to 48
47
Symbol
μSA[7:0]
A
H
B
X
SC
reserved
DT
Cerr[1:0]
reserved
NrBytes
Transferred[11:0]
reserved
DataStart
Address[15:0]
μFrame[7:0]
HubAddress
[6:0]
PortNumber[6:0]
SE[1:0]
reserved
Start and complete split for interrupt: bit description
Access
SW — writes
(0 → 1)
HW — writes
(1 → 0)
After
processing
SW — sets
HW — resets
HW — writes
HW — writes
HW — writes
SW — writes 0
HW — updates
-
HW — writes
SW — writes
HW — writes
SW — writes
-
HW — writes
-
SW — writes
SW — writes
SW — writes
SW — writes
SW — writes
-
-
-
-
-
-
-
-
-
-
Value
-
-
-
-
-
-
-
-
-
Rev. 08 — 13 April 2010
Description
Specifies which μSOF the start split needs to be placed.
For OUT token: When the frame number of bits DW1[7:3]
matches the frame number of the USB bus, these bits are checked
for one before they are sent for the μSOF.
For IN token: Only μSOF0, μSOF1, μSOF2 or μSOF3 can be set
to 1. Nothing can be set for μSOF4 and above.
Active: Write the same value as that in V.
Halt: The Halt bit is set when any microframe transfer status has a
stalled or halted condition.
Babble: This bit corresponds to bit 1 of Status0 to Status7 for
every microframe transfer status.
Transaction Error: This bit corresponds to bit 0 of Status0 to
Status7 for every microframe transfer status.
Start/Complete:
0 — Start split
1 — Complete split
-
Data Toggle: For an interrupt transfer, set correct bit to start the
PTD.
Error Counter: This field corresponds to the Cerr[1:0] field in TD.
00 — The transaction will not retry.
11 — The transaction will retry three times. Hardware will
decrement these values.
-
Number of Bytes Transferred: This field indicates the number of
bytes sent or received for this transaction.
-
Data Start Address: This is the start address for data that will be
sent or received on or from the USB bus. This is the internal
memory address and not the CPU address.
Bits 7 to 3 is the polling rate in milliseconds. Polling rate is defined
as 2
millisecond. See
Hub Address: This indicates the hub address.
Port Number: This indicates the port number of the hub or
embedded TT.
This depends on the endpoint type and direction. It is valid only for
split transactions.
only.
-
(b − 1)
μSOF; where b = 4 to 16. When b is 4, executed every
…continued
Table
Table 84
Embedded Hi-Speed USB host controller
83.
applies to start split and complete split
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