HCPL-0721-500 Avago Technologies US Inc., HCPL-0721-500 Datasheet - Page 11

• Manufacturer Part Number: HCPL-0721-500
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-0721-500

• Number Of Elements: 1
• Forward Voltage: 5.5V
• Output Current: 10mA
• Package Type: SOIC
• Operating Temp Range: -40C to 85C
• Power Dissipation: 150mW
• Propagation Delay Time: 40ns
• Pin Count: 8
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Output Type: Push-Pull
• Isolation Voltage: 3750Vrms
• Lead Free Status / RoHS Status: Not Compliant

Application Information
Bypassing and PC Board Layout
The HCPL-772X/072X optocouplers are extremely easy
to use. No external interface circuitry is required because
the HCPL-772X/072X use high-speed CMOS IC technol-
ogy allowing CMOS logic to be connected directly to the
inputs and outputs.
As shown in Figure 10, the only external components
Figure 10. Recommended printed circuit board layout.
Figure 11. Recommended printed circuit board layout.
Propagation Delay, Pulse-Width Distortion and Propagation Delay
Skew
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a sys-
tem. The propagation delay from low to high (t
amount of time required for an input signal to propa-
gate to the output, causing the output to change from
Figure 12.
11
GND
INPUT
OUTPUT
V
V
DD1
DD1
V
V
1
I
I
V
V
O
I
GND
C1
1
10%
NC
C1, C2 = 0.01 µF TO 0.1 µF
C1
1
2
3
4
90%
HCPL-0710 fig 11
t
PLH
HCPL-0710 fig 13
t
PHL
8
7
6
5
HCPL-0710 fig 12
NC
90%
GND
50%
C2
10%
2
PLH
) is the
V
V
5 V CMOS
0 V
V
2.5 V CMOS
V
DD2
O
OH
OL
required for proper operation are two bypass capaci-
tors. Capacitor values should be between 0.01 µF and
0.1 µF. For each capacitor, the total lead length between
both ends of the capacitor and the power-supply pins
should not exceed 20 mm. Figure 11 illustrates the rec-
ommended printed circuit board layout for the HPCL-
772X/072X.
low to high. Similarly, the propagation delay from high
to low (t
signal to propagate to the output, causing the output to
change from high to low. See Figure 12.
C2
C1, C2 = 0.01 µF TO 0.1 µF
PHL
) is the amount of time required for the input
V
V
GND
DD2
O
2