HCPL7850300 Avago Technologies US Inc., HCPL7850300 Datasheet - Page 6

• Manufacturer Part Number: HCPL7850300
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL7850300

• Operating Supply Voltage (typ): 5V
• Lead Free Status / RoHS Status: Not Compliant

AC Electrical Specifications
Over recommended operating conditions (T
V
Parameter
Common Mode
Rejection
Propagation
Delay to 50%
Propagation
Delay to 90%
Rise/Fall
Time (10-90%)
Small-Signal
Bandwidth
(–3 dB)
Small-Signal
Bandwidth
(–45˚)
RMS Input-
Referred Noise
Power Supply
Rejection
*All typicals are at the nominal operating conditions of V
Notes:
10. Data sheet value is the amplitude of the transient at the differential output of the HCPL-7850 when a 1 V
11. Device considered a two-terminal device: Pins 1, 2, 3, and 4 are shorted together and pins 5, 6, 7, and 8 are shorted together.
12. Commercial parts receive 100% testing at 25˚C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25˚C, +125˚C and –55˚C (Subgroups
13. Parameters are tested as part of device initial characterization and after design and process changes only. Parameters are guaranteed to limits specified
14. The f
DD2
1. If V
2. Exact offset value is dependent on layout of external bypass capacitors. The offset value in the data sheet corresponds to Avago’s recommended
3. Nonlinearity is defined as half of the peak-to-peak output deviation from the best-fit gain line, expressed as a percentage of the full-scale differential
4. Because of the switched capacitor nature of the sigma-delta A/D converter, time averaged values are shown.
5. CMRR
6. When the differential input signal exceeds approximately 320 mV, the outputs will limit at the typical values shown.
7. Short-circuit current is the amount of output current generated when either output is shorted to V
8. CMR (also known as IMR or Isolation Mode Rejection) specifies the minimum rate of rise of a common mode signal applied across the isolation
9. Output noise comes from two primary sources: chopper noise and sigma-delta quantization noise. Chopper noise results from chopper stabilization of
6
layout (see Figures 26 and 27).
output voltage.
both pins 2 and 3 with respect to pin 4.
operations under these conditions.
boundary at which small output perturbations begin to occur. These output perturbations can occur with both the rising and falling edges of the
common mode waveform and may be of either polarity. A CMR failure is defined as a perturbation exceeding 200 mV at the output of the recommended
application circuit (Figure 24). See Applications section for more information on CMR.
the output op-amps. It occurs at a specific frequency (typically 500 kHz) and is not attenuated by the on-chip output filter. The on-chip filter does
eliminate most, but not all, of the sigma-delta quantization noise. An external filter circuit may be easily added to the external post-amplifier to reduce
the total RMS output noise. See Applications section for more information.
fall times (measured at pins 1 and 8) is applied to both V
1 and 9, 2 and 10, 3 and 11, respectively).
for all lots not specifically tested.
= 5 V, unless otherwise specified).
IN–
-3dB
IN
is brought above V
is defined as the ratio of the gain for differential inputs applied between pins 2 and 3 to the gain for both common mode inputs applied to
test is guaranteed by the T
Symbol
CMR
t
t
t
f
f
V
PSR
–3 dB
–45˚
PD50
PD90
R/F
N
DD1
–2 V with respect to GND1 an internal test mode may be activated. This test mode is not intended for customer use.
Group A
Subgroups
9
9,10,11
9,10,11
9,10,11
9,10,11
RISE
test.
[12]
A
= –55˚C to +125˚C, V
IN+
Min.
5
45
DD1
= 0 V, V
and V
Typ.*
8
5.7
100
31
0.6
570
3.7
3.4
IN–
DD2
= 0 V, T
.
Max. Units
7.5
11.0
7.5
A
= 25˚C, V
IN+
kV/ s
kHz
mV
mV
= 0 V, V
s
DD1
rms
P–P
= 5 V and V
IN–
Test Conditions
V
4.5 V (V
V
4.5 V (V
4.5 V (V
V
sine wave
In recommended
application circuit
CM
IN+
IN+
= 0 V, V
5.5 V, T
5.5 V
5.5 V
= 1 kV
= 0 to 100 mV step
= 200 mVpk-pk
DD2
DD2
P–P
= 5 V.
or ground. Avago does not recommend
, 1 MHz square wave with 100 ns rise and
DD1
A
DD1
DD1
DD1
= 25˚C
, V
, V
, V
= 5 V and
DD2
DD2
DD2
)
)
)
Fig.
16
18,19
18,20, 14
21
22,24 9
Note
8,13
10