JGB-10SNAA1 JDS UNIPHASE, JGB-10SNAA1 Datasheet - Page 14

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JGB-10SNAA1

Manufacturer Part Number
JGB-10SNAA1
Description
Manufacturer
JDS UNIPHASE
Datasheet

Specifications of JGB-10SNAA1

Lead Free Status / RoHS Status
Not Compliant
JGB-10SNAA1
JGB-10SYAA1
Fibre Channel GBIC
Control Electrical Interface
Page 14 of 29
Voltage Levels
TTL Outpu)
TTL Input
Serial ID SCL and SDA lines
Timing Characteristics
Tx_Disable (assert time)
Tx_Disable (de-assert time)
Tx_Disable (time to start reset)
Initialization Time (Tx_Fault)
Tx_Fault Assert Delay
Rx_LOS Assert Delay
Rx_LOS De-Assert Delay
1. A 4.7-10 k
2. A 10 k
3. See “Tx_Disable” on page 7.
4. See “Resetting a Fault (Tx_Fault)” on page 8.
5. See “Tx_Fault” on page 6 and “Tx_Disable” on page 7 for additional timing information.
6. See “Rx_LOS” on page 6 for timing relations.
pull-up resistor to V
pull-up resistor to V
JGB-10LNAA1
JGB-10LYAA1
Parameter
DD
T is present on the GBIC (-1mA max).
DD
T is required.
t_loss_on
t_loss_off
Symbol
t_reset
t_fault
t_init
t_off
t_on
V
V
V
V
V
V
OH
OL
IH
IH
IL
IL
host_V
V
DD
Min
0.0
2.0
T x 0.7
10
0
CC
- 0.5
host_V
V
V
V
DD
DD
DD
0.50
Max
300
100
100
100
0.8
T + 0.3
T + 0.5
T x 0.3
10
CC
1
+ 0.3
Units
ms
ms
V
V
V
V
V
V
s
s
s
s
s
GBIC.1063
03/06/02
Notes
1
2
1
3
3
3
4
5
6
6

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