LM1881M/HALF National Semiconductor, LM1881M/HALF Datasheet - Page 3

• Manufacturer Part Number: LM1881M/HALF
• Manufacturer: National Semiconductor

Specifications of LM1881M/HALF

• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics LM1881
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For guaranteed specifications and test conditions, see the
Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
Note 2: For operation in ambient temperatures above 25˚C, the device must be derated based on a 150˚C maximum junction temperature and a package thermal
resistance of 110˚C/W, junction to ambient.
Note 3: ESD susceptibility test uses the “human body model, 100 pF discharged through a 1.5 kΩ resistor”.
Note 4: Machine Model, 220 pF – 240 pF discharged through all pins.
Note 5: Typicals are at T
Note 6: Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.
Note 7: Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1, 3, 5 and 7) to the R
Note 8: Delay time between the start of vertical sync (at input) and the vertical output pulse.
Typical Performance Characteristics
R
vs Vertical Serration
J
Gate Time vs R
SET
Burst/Black Level
= 25˚C and represent the most likely parametric norm.
Pulse Separation
Value Selection
SET
00915007
00915009
(Continued)
3
Sync Delay Time
Vertical Default
Width vs R
Vertical Pulse
vs R
SET
SET
SET
pin (Pin 6).
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00915008
00915010