MCIMX27MJP4A Freescale, MCIMX27MJP4A Datasheet - Page 27

• Manufacturer Part Number: MCIMX27MJP4A
• Manufacturer: Freescale

Specifications of MCIMX27MJP4A

• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
MA10
A [25:14]
SDBA[1:0]
SD[31:0]
SDQS[3:0]
DQM0–DQM3
EB0
EB1
OE
CS [5:0]
ECB
LBA
BCLK
RW
RAS
CAS
SDWE
SDCKE0
SDCKE1
SDCLK
SDCLK_B
NFWE_B
NFRE_B
NFALE
NFCLE
NFWP_B
NFCE_B
NFRB
Pad Name
Table 3. i.MX27/MX27L Signal Descriptions (continued)
Address bus signals for SDRAM/MDDR
Address bus signals, shared with WEIM and PCMCIA
SDRAM/MDDR bank address signals
Data bus signals for SDRAM, MDDR
MDDR data sample strobe signals
SDRAM data mask strobe signals
Active low external enable byte signal that controls D [15:8], shared with PCMCIA PC_REG.
Active low external enable byte signal that controls D [7:0], shared with PCMCIA PC_IORD.
Memory Output Enable—Active low output enables external data bus, shared with PCMCIA
PC_IOWR.
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected
by the Function Multiplexing Control Register (FMCR) in the System Control chapter. By default
CSD [1:0] is selected. DTACK is multiplexed with CS4.
CS[5:4] are multiplexed with ETMTRACECLK and ETMTRACESYNC; PF22, 21.
an on-going burst sequence and initiate a new (long first access) burst sequence.
Active low signal sent by flash device causing external burst device to latch the starting burst
address.
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal
is also shared with the PCMCIA PC_WE.
SDRAM/MDDR Row Address Select signal
SDRAM/MDDR Column Address Select signal
SDRAM Write Enable signal
SDRAM Clock Enable 0
SDRAM Clock Enable 1
SDRAM Clock
SDRAM Clock_B
NFC Write enable signal, multiplexed with ETMPIPESTAT2; PF6
NFC Read enable signal, multiplexed with ETMPIPESTAT1; PF5
NFC Address latch signal, multiplexed with ETMPIPESTAT0; PF4
NFC Command latch signal, multiplexed with ETMTRACEPKT0; PF1
NFC Write Permit signal, multiplexed with ETMTRACEPKT1; PF2
NFC Chip enable signal, multiplexed with ETMTRACEPKT2; PF3
NFC read Busy signal, multiplexed with ETMTRACEPKT3; PF0
Active low input signal sent by flash device to the EIM whenever the flash device must terminate
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Function/Notes
Signal Descriptions
27