HSP43216VC-52 Intersil, HSP43216VC-52 Datasheet - Page 8

no-image

HSP43216VC-52

Manufacturer Part Number
HSP43216VC-52
Description
Manufacturer
Intersil
Datasheet

Specifications of HSP43216VC-52

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HSP43216VC-52Z
Manufacturer:
Intersil
Quantity:
10 000
Operational Modes
Decimate By 2 Filter Mode (Mode1-0 = 00)
The concept of operation for Decimate by Two Filter mode is
most easily understood by comparing the 7 tap transversal
filter implementation to the equivalent polyphase
implementation. The transversal implementation is shown in
Figure 5.
By inspecting the sum-of-products for the decimated output
in Figure 5, it is seen that even indexed input samples are
always multiplied by the even filter coefficients and the odd
samples are always multiplied by the odd coefficients. This
computational partitioning is realized in the polyphase
implementation shown in Figure 6.
Indicates samples discarded by decimation process
X3,X2,X1,X0
FIGURE 5. TRANSVERSAL IMPLEMENTATION OF
RND
000
001
010
011
100
101
110
2-0
111
Y(0) = X0(C0)+X1(C1)+X2(C2)+X3(C3)+X4(C4)+X5(C5)+X6(C6)
Y(1) = X1(C0)+X2(C1)+X3(C2)+X4(C3)+X5(C4)+X6(C5)+X7(C6)
Y(2) = X2(C0)+X3(C1)+X4(C2)+X5(C3)+X6(C4)+X7(C5)+X8(C6)
Y(3) = X3(C0)+X4(C1)+X5(C2)+X6(C3)+X7(C4)+X8(C5)+X9(C6)
TABLE 5. OUTPUT ROUNDING CONTROL
Round output to 8-bits, AOUT15-8 and BOUT15-8, zero
lower bits.
Round output to 9-bits, AOUT15-7 and BOUT15-7, zero
lower bits.
Round output to 10-bits, AOUT15-6 and BOUT15-6,
zero lower bits.
Round output to 11-bits, AOUT15-5 and BOUT15-5,
zero lower bits.
Round output to 12-bits, AOUT15-4 and BOUT15-4,
zero lower bits.
Round output to 14-bits, AOUT15-2 and BOUT15-2,
zero lower bits.
Round output to 16-bits, AOUT15-0 and BOUT15-0.
Zero all outputs.
DECIMATE BY 2 HALFBAND FILTER
C0 C1 C2 C3 C4 C5 C6
ROUND FUNCTION
8
...,Y1,Y0
2
..,Y4,Y2,Y0
HSP43216
In the polyphase implementation, the input data is broken into
even and odd sample streams which are processed by a set
of polyphase filters running at one half of the input data rate.
These filters are designated as even or odd tap filters
depending upon whether the coefficients were derived from
the even or odd indexed coefficients of the original transversal
filter. This architecture only produces the outputs which are
not discarded by the decimation process. NOTE: Since the
only non-zero tap for a halfband filter is the center tap,
the Odd Tap Filter reduces to a delay and multiply
operation.
The operation of the HSP43216 in Decimate by Two mode is
analogous to the polyphase implementation in Figure 6. In
this mode, the internal data paths are routed as shown in
Figure 7A and Figure 7B. The different data flows depend on
whether internal or external multiplexing has been selected
using the INT/EXT control input. In either case, an input data
stream is decomposed into even and odd sample streams
which are then routed to the even and odd tap polyphase
filters. The output of each polyphase filter is summed and
output via AOUT0-15.
FIGURE 6. POLYPHASE IMPLEMENTATION OF DECIMATE
Y(0) = X0(C0)+X1(C1)+X2(C2)+X3(C3)+X4(C4)+X5(C5)+X6(C6)
Y(1) = X2(C0)+X3(C1)+X4(C2)+X5(C3)+X6(C4)+X7(C5)+X8(C6)
...,X5,X3,X1
...,X4,X2,X0
BY 2 HALFBAND FILTER
EVEN TAP FILTER
ODD TAP FILTER
R
E
G
C0 C2 C4 C6
C1 C3 C5
+
..,Y2,Y1,Y0
October 6, 2008
FN3365.10

Related parts for HSP43216VC-52