STK25C48-W25 Cypress Semiconductor Corp, STK25C48-W25 Datasheet
STK25C48-W25
Specifications of STK25C48-W25
Related parts for STK25C48-W25
STK25C48-W25 Summary of contents
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... AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM Obsolete - Not Recommend for new Designs DESCRIPTION The STK25C48 is a fast incorporated in each static memory cell. The be read and written an unlimited number of times, while independent nonvolatile data resides in the Elements tile Elements matically on power down using charge stored in system capacitance ...
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... STK25C48 ABSOLUTE MAXIMUM RATINGS Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V Voltage on Input Relative –0. Voltage –0. 0-7 Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration 15mA DC CHARACTERISTICS ...
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... March 2006 PARAMETER ; device is continuously selected AVAV 3 t AVQV 5 t AXQX AVAV 1 t ELQV 6 t ELQX 4 t GLQV 8 t GLQX 10 t ELICCH ACTIVE 3 Document Control # ML0005 rev 0.2 STK25C48 ± 5.0V CC STK25C48-25 STK25C48-35 STK25C48-45 MIN MAX MIN MAX MIN MAX DATA VALID 11 t ...
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... ELWH 17 t AVWH 13 t WLWH 15 t DVWH DATA VALID 20 t WLQZ HIGH IMPEDANCE AVAV 14 t ELEH AVEH 13 t WLEH 15 t DVEH DATA VALID HIGH IMPEDANCE 4Document Control # ML0005 rev 0.2 ± 5.0V 10%) CC STK25C48-35 STK25C48-45 UNITS MAX MIN MAX MIN MAX ...
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... DELAY BROWN OUT AutoStore™ NO RECALL NO RECALL (V DID NOT GO DID NOT GO CC BELOW V ) RESET RESET 5 Document Control # ML0005 rev 0.2 STK25C48 (V = 5.0V ± 10%) CC STK25C48 UNITS MIN MAX 550 4.0 4.5 3 STORE BROWN OUT AutoStore™ RECALL WHEN V RETURNS CC ) ABOVE V ...
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... STK25C48 The STK25C48 is a versatile memory chip that pro- vides several modes of operation. The STK25C48 can operate as a standard Nonvolatile Elements shadow to which the information can be copied, or from which the SRAM can be updated in nonvolatile mode. SRAM NOISE CONSIDERATIONS Note that the STK25C48 is a high-speed memory and so must have a high-frequency bypass capaci- tor of approximately 0.1μ ...
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... Cycle Time (ns) Figure 2: I (max) Reads CC March 2006 100 TTL 20 CMOS 0 200 7 Document Control # ML0005 rev 0.2 STK25C48 TTL CMOS 50 100 150 200 Cycle Time (ns) Figure 3: I (max) Writes CC ...
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... STK25C48 STK25C48 March 2006 ORDERING INFORMATION - Temperature Range Access Time Lead Finish Package 8Document Control # ML0005 rev 0.2 Blank = Commercial (0 to 70° Industrial (–40 to 85° 25ns 35 = 35ns 45 = 45ns Blank = 85%Sn/15% 100% Sn (Matte Tin Plastic 24-pin 600 mil DIP ...
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... Document Revision History Date Revision December 2002 0.0 September 2003 0.1 March 2006 0.2 March 2006 Summary Removed 20 nsec device. Added lead-free lead finish Marked as Obsolete, Not recommended for new design. 9 Document Control # ML0005 rev 0.2 STK25C48 ...
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... STK25C48 March 2006 10Document Control # ML0005 rev 0.2 ...