STK16C68-W45I Cypress Semiconductor Corp, STK16C68-W45I Datasheet - Page 7

• Manufacturer Part Number: STK16C68-W45I
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK16C68-W45I

• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 5V
• Package Type: PDIP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -40C to 85C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 65mA
• Lead Free Status / RoHS Status: Not Compliant

The AutoStorePlus™ STK16C68 is a fast 8K x 8
SRAM that does not lose its data on power-down.
The data is preserved in integral QuantumTrap™
Nonvolatile Elements while power is unavailable.
The nonvolatility of the STK16C68 does not require
any system intervention or support: AutoStore-
Plus™ on power-down and automatic RECALL on
power-up guarantee data integrity without the use of
batteries.
NOISE CONSIDERATIONS
Note that the STK16C68 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1μF connected between V
and V
possible. As with all high-speed
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK16C68 performs a
and G are low and W is high. The address specified
on pins A
bytes will be accessed. When the
by an address transition, the outputs will be valid
after a delay of t
initiated by E or G, the outputs will be valid at t
at t
outputs will repeatedly respond to address changes
within the t
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high or W is brought low.
SRAM WRITE
A
low. The address inputs must be stable prior to
entering the
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W controlled
E controlled
It is recommended that G be kept high during the
entire
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
March 2006
WRITE
GLQV
SS
, whichever is later (
WRITE
, using leads and traces that are as short as
cycle is performed whenever E and W are
0-12
AVQV
WRITE
WRITE
cycle to avoid data bus contention on
determines which of the 8,192 data
access time without the need for tran-
AVQV
WRITE
.
(
cycle and must remain stable
READ
or t
READ
cycle #1). If the
READ
DVEH
WLQZ
before the end of an
cycle #2). The data
DVWH
CMOS
cycle whenever E
after W goes low.
READ
DEVICE OPERATION
before the end
0-7
ICs, normal
will be writ-
is initiated
READ
ELQV
or
CC
is
7
AutoStorePlus™ OPERATION
The STK16C68’s automatic
is completely transparent to the system. The
AutoStore™ initiation takes less than 500ns when
power is lost (V
depends only on its internal capacitor for
completion. This safe transfer of data from
Nonvolatile Elements takes place regardless of
power supply slew rate.
In order to prevent unneeded
automatic
WRITE
recent
STORE
or not a
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of V
be initiated and will take t
If the STK16C68 is in a
power-up
To help avoid this situation, a 10kΩ resistor should
be connected either between W and system V
between E and system V
SOFTWARE NONVOLATILE STORE
The STK16C68 software
executing sequential
address locations. During the
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the
nonvolatile memory. Once a
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of
addresses is used for
tant that no other
vene in the sequence or the sequence will be
aborted and no
To initiate the software
READ
CC
< V
Document Control # ML0010 rev 0.2
sequence must be performed:
STORE
operation has taken place since the most
cycles are performed regardless of whether
WRITE
RESET
RECALL
STORE
SWITCH
), an internal
operation has taken place.
or
STORE
CC
CC
, a
will be ignored unless at least one
, the
< V
RECALL
READ
once again exceeds the sense
RECALL
READ
SWITCH
SRAM
STORE
or
STORE
CC
RESTORE
WRITE
STORE
or
RECALL
.
) at which point the part
cycle. Software-initiated
RECALL
cycles from six specific
STORE
WRITE
cycle will automatically
READ
STORE
data will be corrupted.
STORE
STORE
initiation, it is impor-
to complete.
cycle, the following
state at the end of
cycle is initiated by
will take place.
s from specific
SRAM
on power-down
accesses inter-
request will be
STK16C68
operations, the
cycle an erase
cycle is initi-
data into
SRAM
STORE
CC
or
to