STK15C88-W45 Cypress Semiconductor Corp, STK15C88-W45 Datasheet - Page 4

• Manufacturer Part Number: STK15C88-W45
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK15C88-W45

• Word Size: 8b
• Organization: 32Kx8
• Density: 256Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 5V
• Package Type: PDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 70mA
• Lead Free Status / RoHS Status: Not Compliant

Document Number: 001-50593 Rev. *A
Device Operation
The STK15C88 is a versatile memory chip that provides
several modes of operation. The STK15C88 can operate as a
standard 32K x 8 SRAM. It has a 32K x 8 nonvolatile element
shadow to which the SRAM information can be copied, or from
which the SRAM can be updated in nonvolatile mode.
SRAM Read
The STK15C88 performs a READ cycle whenever CE and OE
are LOW while WE is HIGH. The address specified on pins
A
READ is initiated by an address transition, the outputs are
valid after a delay of t
initiated by CE or OE, the outputs are valid at t
whichever is later (READ cycle 2). The data outputs
repeatedly respond to address changes within the t
time without the need for transitions on any control input pins,
and remains valid until another address change or until CE or
OE is brought HIGH.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW.
The address inputs must be stable prior to entering the WRITE
cycle and must remain stable until either CE or WE goes HIGH
at the end of the cycle. The data on the common I/O pins
DQ
end of a WE controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE
cycle to avoid data bus contention on common I/O lines. If OE
is left LOW, internal circuitry turns off the output buffers t
after WE goes LOW.
AutoStore Operation
The STK15C88 uses the intrinsic system capacitance to
perform an automatic STORE on power down. As long as the
system power supply takes at least t
V
ically store the SRAM data in nonvolatile elements on power
down.
In order to prevent unneeded STORE operations, automatic
STOREs will be ignored unless at least one WRITE operation
has taken place since the most recent STORE or RECALL
cycle. Software initiated STORE cycles are performed
regardless of whether a WRITE operation has taken place.
Hardware RECALL (Power Up)
During power up or after any low power condition (V
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t
If the STK15C88 is in a WRITE state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system V
0–14
SWITCH
RESET
0–7
determines the 32,768 data bytes accessed. When the
are written into the memory if it has valid t
), an internal RECALL request is latched. When V
down to 3.6V, the STK15C88 will safely and automat-
CC
or between CE and system V
AA
(READ cycle 1). If the READ is
STORE
HRECALL
SWITCH
CC
ACE
to decay from
SD
.
to complete.
, a RECALL
, before the
or at t
AA
access
HZWE
CC
DOE
CC
<
,
Software STORE
Data is transferred from the SRAM to the nonvolatile memory
by a software address sequence. The STK15C88 software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact
order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed, followed by a program of
the nonvolatile elements. When a STORE cycle is initiated,
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence. If they
intervene, the sequence is aborted and no STORE or RECALL
takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
The software sequence is clocked with CE controlled READs.
When the sixth address in the sequence is entered, the
STORE cycle commences and the chip is disabled. It is
important that READ cycles and not WRITE cycles are used
in the sequence. It is not necessary that OE is LOW for a valid
sequence. After the t
again activated for READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner
similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE controlled READ
operations is performed:
Internally, RECALL is a two step procedure. First, the SRAM
data is cleared, and then the nonvolatile information is trans-
ferred into the SRAM cells. After the t
SRAM is once again ready for READ and WRITE operations.
The RECALL operation does not alter the data in the nonvol-
atile elements. The nonvolatile data can be recalled an
unlimited number of times.
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
STORE
cycle time is fulfilled, the SRAM is
RECALL
STK15C88
cycle time, the
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