MT18JSF51272AY-1G1A1 Micron Technology Inc, MT18JSF51272AY-1G1A1 Datasheet - Page 4

• Manufacturer Part Number: MT18JSF51272AY-1G1A1
• Manufacturer: Micron Technology Inc

Specifications of MT18JSF51272AY-1G1A1

• Main Category: DRAM Module
• Sub-category: DDR3 SDRAM
• Module Type: 240UDIMM
• Device Core Size: 72b
• Organization: 512Mx72
• Total Density: 4GByte
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Operating Current: 2.475A
• Number Of Elements: 18
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

Table 6:
PDF: 09005aef83014429/Source: 09005aef83014466
JSF18C256_512x72A.fm - Rev. C 5/08 EN
RAS#, CAS#, WE#
CK0, CK0#,
CK1, CK1#
DQS#[8:0]
DQS[8:0],
ODT[1:0]
DQ[63:0]
Symbol
CKE[1:0]
DM[8:0]
A[13:0],
EVENT#
A[14:0]
BA[2:0]
RESET#
SA[2:0]
CB[7:0]
S#[1:0]
2GB
4GB
SDA
V
SCL
DD
Pin Descriptions
(open drain)
(LVCMOS)
Output
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands. The address inputs also provide the op-code during the mode
register command set
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of the DQS. Although the DM pins are input-only, the DM loading is
designed to match that of the DQ and DQS pins.
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will
be ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: RESET# is an active LOW CMOS input referenced to V
is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
LOW ≤ 0.2 × V
applications will most likely be unterminated, heavily loaded, and have very slow slew
rates. A slow slew rate receiver design is recommended along with implementing on-
chip noise filtering to prevent false triggering (RESET# assertion minimum pulse width is
100ns).
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: These pins are used to configure the temperature sensor/SPD
EEPROM address range on the I
Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize the
communication to and from the temperature sensor/SPD EEPROM.
Check bits: Data used for ECC.
Data input/output: Bidirectional data bus.
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out
of the temperature sensor/SPD EEPROM on the module on the I
Temperature event: The EVENT# pin is asserted by the temperature sensor when
critical temperature thresholds have been exceeded.
Power supply: 1.5V ±0.075V. The component V
module V
DD
.
2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM UDIMM
DD
Q. RESET# assertion and deassertion are asynchronous. System
.
4
2
C bus.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
DD
and V
DD
SS
Q are connected to the
. The RESET# input receiver
©2008 Micron Technology, Inc. All rights reserved
2
C bus.
DD
Q and DC