M471B5673EH1-CF8 Samsung Semiconductor, M471B5673EH1-CF8 Datasheet - Page 21

• Manufacturer Part Number: M471B5673EH1-CF8
• Manufacturer: Samsung Semiconductor

Specifications of M471B5673EH1-CF8

• Main Category: DRAM Module
• Sub-category: DDR3 SDRAM
• Module Type: 204SODIMM
• Device Core Size: 64b
• Organization: 256Mx64
• Total Density: 2GByte
• Chip Density: 1Gb
• Access Time (max): 20ns
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Operating Current: 1.16A
• Number Of Elements: 16
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 204
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
g) IDD current measure method and detail patterns are described on DDR3 component datasheet
Unbuffered SoDIMM
IDD6ET
IDD6TC
IDD7
Symbol
Description
Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled
LOW; CL: AC Timing Table ; BL: 8
ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Auto Self-Refresh Current (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Enabled
LOW; CL: AC Timing Table ; BL: 8
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: AC Timing Table; BL: 8
mand, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0;
Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output Buffer and RTT: Enabled in Mode Reg-
isters
b)
; ODT Signal: stable at 0
a)
a)
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Extended Tempera-
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING; DM:stable at 0; Bank Activity: Auto
f)
d)
d)
; Self-Refresh Temperature Range (SRT): Normal
; Self-Refresh Temperature Range (SRT): Extended
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f)
b)
; ODT Signal: FLOATING
b)
; ODT Signal: FLOATING
a)
; AL: CL-1; CS: High between ACT and RDA; Com-
e)
; CKE: Low; External clock: Off; CK and CK:
e)
Rev. 1.0 February 2009
; CKE: Low; External clock: Off; CK and CK:
DDR3 SDRAM