KHX13000D3LLK2/2G KINGSTON TECHNOLOGY, KHX13000D3LLK2/2G Datasheet

KHX13000D3LLK2/2G

Manufacturer Part Number

KHX13000D3LLK2/2G

Description

Manufacturer

KINGSTON TECHNOLOGY

Datasheet

1.KHX13000D3LLK22G.pdf (2 pages)

Specifications of KHX13000D3LLK2/2G

Main Category

DRAM Module

Sub-category

DDR3 SDRAM

Module Type

240DIMM

Device Core Size

64b

Organization

128Mx64x2

Total Density

2GByte

Chip Density

1Gb

Maximum Clock Rate

1.066GHz

Operating Supply Voltage (typ)

1.5V

Number Of Elements

Operating Supply Voltage (max)

1.575V

Operating Supply Voltage (min)

1.425V

Operating Temp Range

0C to 85C

Operating Temperature Classification

Commercial

Pin Count

240

Mounting

Socket

Lead Free Status / RoHS Status

Supplier Unconfirmed

Current page: 1 of 2
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Document No. 4804858-001.A00

DESCRIPTION:

Kingston's KHX13000D3ULK2/2G is a kit of two 128M x 64-bit 1GB (1024MB) DDR3-1625 CL7 SDRAM (Synchro-

nous DRAM) memory modules, based on eight 128M x 8-bit DDR3 FBGA components per module. Each module pair

has been tested to run at DDR3-1625MHz at a low latency timing of 7-7-7 at 1.9V. The SPDs are programmed to JEDEC

standard latency DDR3-1066Mhz timing of 7-7-7 at 1.5V. Each 240-pin DIMM uses gold contact fingers and requires

+1.5V. The JEDEC standard electrical and mechanical specifications are as follows:

FEATURES:

PERFORMANCE:

T E C H N O L O G Y

JEDEC standard 1.5V ± 0.075V Power Supply

VDDQ = 1.5V ± 0.075V

533MHz fCK for 1066Mb/sec/pin

8 independent internal bank

Programmable CAS Latency: 5,6,7,8,9,10

Posted CAS

Programmable Additive Latency: 0, CL - 2, or CL - 1 clock

Programmable CAS Write Latency(CWL) = 7(DDR3-1066)

8-bit pre-fetch

Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4

which does not allow seamless read or write [either on the fly using A12 or MRS]

Bi-directional Differential Data Strobe

Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)

On Die Termination using ODT pin

Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE . 95°C

Asynchronous Reset

1066Mbps CL7 doesn’t have backward compatibility with 800Mbps CL5

PCB : Height 1.180” (30.00mm), single sided component

CL(IDD)

Row Cycle Time (tRCmin)

Refresh to Active/Refresh Command Time (tRFCmin)

Row Active Time (tRASmin)

Power

UL Rating

Operating Temperature

Storage Temperature

2GB (1GB 128M x 64-Bit x 2 pcs.) PC3-13000

KHX13000D3LLK2/2G

CL7 240-Pin DIMM Kit

K E

Y E

12/10/07

7 cycles

50.63ns (min.)

110ns

37.5ns (min.)

TBD W (operating per module)

94 V - 0

-55

C to 85

C to +100

Page 1

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KHX13000D3LLK2/2G Summary of contents

Page 1

... PCB : Height 1.180” (30.00mm), single sided component PERFORMANCE: CL(IDD) Row Cycle Time (tRCmin) Refresh to Active/Refresh Command Time (tRFCmin) Row Active Time (tRASmin) Power UL Rating Operating Temperature Storage Temperature Document No. 4804858-001.A00 KHX13000D3LLK2/2G CL7 240-Pin DIMM Kit 7 cycles 50.63ns (min.) 110ns 37.5ns (min.) TBD W (operating per module ...

Page 2

... MODULE DIMENSIONS Units: millimeters Document No. 4804858-001.A00 ValueRAM Page 2 ...

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