MT36VDDF25672Y-40BF3 Micron Technology Inc, MT36VDDF25672Y-40BF3 Datasheet - Page 5
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MT36VDDF25672Y-40BF3
Manufacturer Part Number
MT36VDDF25672Y-40BF3
Description
MODULE DDR SDRAM 2GB 184DIMM
Manufacturer
Micron Technology Inc
Series
-r
Datasheet
1.MT36VDDF25672Y-40BF3.pdf
(20 pages)
Specifications of MT36VDDF25672Y-40BF3
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
256Mx72
Total Density
2GByte
Chip Density
512Mb
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
3.6A
Number Of Elements
36
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Memory Type
DDR SDRAM
Memory Size
2GB
Speed
400MT/s
Features
-
Package / Case
184-RDIMM
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT36VDDF25672Y-40BF3
Manufacturer:
IXYS
Quantity:
219
Table 6:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
RAS#, CAS#, WE#
DQS0–DQS17
CKE0, CKE1
DQ0–DQ63
CK0, CK0#
V
BA0, BA1
SA0–SA2
CB0–CB7
Symbol
S0#, S1#
A0–A12
RESET#
DD
V
Pin Descriptions
SDA
DDSPD
V
SCL
V
NC
/V
REF
SS
DD
Q
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
–
Description
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command.
Bank address: BA0 and BA1 define the device bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Clock: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and the
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and CKE disables (registered
LOW) the internal clock, input buffers, and output drivers.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW.
This signal can be used during power-up to ensure that CKE is LOW and DQ are
High-Z.
Chip selects: S# enables (registered LOW) and disables (registered HIGH) the
command decoder.
Presence-detect address inputs: These pins are used to configure the SPD
EEPROM address range on the I
Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect
data transfer to and from the module.
Check bits.
Data input/output: Data bus.
Data strobe: Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data. Used to capture data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into
and out of the presence-detect portion of the module.
Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
SPD EEPROM power supply: +2.3V to +3.6V.
SSTL_2 reference voltage (V
Ground.
No connect: These pins are not connected on the module.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
/2).
Pin Assignments and Descriptions
2
C bus.
©2002 Micron Technology, Inc. All rights reserved.