MT45W512KW16PGA-70 WT Micron Technology Inc, MT45W512KW16PGA-70 WT Datasheet - Page 10

• Manufacturer Part Number: MT45W512KW16PGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W512KW16PGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Figure 8:
Deep Power-Down (DPD) Operation
PDF: 09005aef8220472e/Source: 09005aef8220461e
8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN
Software Access PAR Functionality
DPD operation disables all refresh-related activity. This mode is used when the system
does not require the storage provided by the PSRAM device. Any stored data will become
corrupted when DPD is entered. When refresh activity has been re-enabled, the PSRAM
device will require 150µs to perform an initialization procedure before normal opera-
tions can resume. READ and WRITE operations are ignored during DPD operation.
The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0).
DPD is initiated by bringing ZZ# to the LOW state for longer than 10µs. Returning ZZ# to
HIGH will cause the device to exit DPD and begin a 150µs initialization process. During
this 150µs period, the current consumption will be higher than the specified standby
levels but considerably lower than the active current specification.
Driving ZZ# LOW will place the device in the PAR mode if the SLEEP bit in the CR has
been set HIGH (CR[4] = 1).
The device should not be put into DPD using CR software access.
NO
PAR permanently
independent of
To enable PAR,
bring ZZ# LOW
Change to ZZ#
functionality.
executed?
Power-Up
ZZ# level.
for 10µs.
Software
enabled,
LOAD
YES
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8Mb: 512K x 16 Async/Page PSRAM
Low-Power Operation
©2006 Micron Technology, Inc. All rights reserved.
Advance