MMDOE28G5MPP-0VA Samsung Semiconductor, MMDOE28G5MPP-0VA Datasheet - Page 14

• Manufacturer Part Number: MMDOE28G5MPP-0VA
• Manufacturer: Samsung Semiconductor

Specifications of MMDOE28G5MPP-0VA

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.0 Shadow Register Block registers Description
6.1 Command Register
This register contains the command code being sent to the device. Command execution begins immediately after this register is written. All
other registers required for the command must be set up before writing the Command Register.
6.2 Device Control Register
This register contains the command code being sent to the device. Command execution begins immediately after this register is written. All
other registers required for the command must be set up before writing the Command Register.
6.2.1 Field / bit description
• HOB is defined by the 48bit Address feature set. A write to any Command register shall clear the HOB bit to zero.
• SRST is the host software reset bit. SRST=1 indicates that the drive is held reset and sets BSY bit in Status register. Setting SRST=0 re-
enables the device.
• nIEN is the enable bit for the device Assertion of INTRQ to the host. When nIEN=0, and the device is selected by Drice select bit in DEVICE/
HEAD register, device interrupt to the host is enabled. When this bit is set, the "I’ bit in the Register Host to Device, PIO setup, Set Device Bits
and DMA Set Up will be set, whether pending interrup is found or not.
6.3 Device / Head Register
6.3.1 Field / bit description
The content of this register shall take effect when written.
• L : Binary encoded address mode select. When L=0, addressing is by CHS mode. When L=1, addressing is by LBA mode.
• DEV: Device select. Cleared to zero selects Device 0. Set to one selects Device1.
• HS3, HS2, HS1, HS0 : Head select bits. The HS3 through HS0 contain bits 24-27 of the LBA. At command completion, these bits are
updated to reflect the current LBA bits 24-27.
MMCRE64G5MPP-0VA
HOB
7
7
-
6
-
6
L
5
-
5
-
4
-
DEV
4
14
3
-
HS3
3
SRST
HS2
2
2
nIEN
HS1
1
1
HS0
0
0
0
Final