SLCF2GBJI STEC, SLCF2GBJI Datasheet - Page 29
![no-image](/images/no-image-200.jpg)
SLCF2GBJI
Manufacturer Part Number
SLCF2GBJI
Description
Manufacturer
STEC
Type
CompactFlashr
Datasheet
1.SLCF2GBJI.pdf
(47 pages)
Specifications of SLCF2GBJI
Density
2GByte
Operating Supply Voltage (typ)
3.3/5V
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Package Type
Not Required
Mounting
Socket
Pin Count
50
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
3.18/4.75V
Operating Supply Voltage (max)
3.465/5.25V
Programmable
Yes
Lead Free Status / RoHS Status
Not Compliant
SLCFxxxJ(T2)(I)
CONFIGURATION REGISTER
SPECIFICATION
This card supports four configuration registers for the
purpose of the configuration and observation of the card.
These registers can be used in memory card mode and I/O
card mode. In True IDE mode, these registers can not be
used.
Configuration Option Register
(Address 200h)
This register is used to configure and observe the status of
the card, and to issue soft resets to the card.
Initial Value: 00h
Name
SRESET (HOST->)
LevlREQ (HOST->) R/W
INDEX (HOST->)
5
0
0
0
0
SRESET
bit7
4
0
0
0
0
INDEX bit
3
0
0
0
0
LevlREQ
2
0
0
0
0
bit6
R/W
R/W
1
R/W
0
0
1
1
0
0
1
0
1
Function
Setting this bit to “1” places the card in the reset state. This operation is equal to a hard
reset, except this bit is not cleared.
This bit is set to “0” when pulse mode interrupt is selected, and to “1” when level mode
interupt is selected.
These bits are used to select the operation mode of the card. (See table below.) At power on,
hard reset, and soft reset, this data is “000000” for the purpose of Memory card interface
recognition, and access to CIS.
bit5
Card Mode
Memory Card
I/O Card
I/O Card
I/O Card
bit4
INDEX (bits 0-5)
Task File Register Address Mapping Mode
0h to Fh, 400h to 7FFh
xx0h to xxFh
1F0h to 1F7h, 3F6h to 3F7h
170h to 177h, 376h to 377h
bit3
Document Part Number 61000-02805-111 March 2005
bit2
bit1
COMPACTFLASH
Memory Mapped
Contiguous I/O Mapped
Primary I/O Mapped
Secondary I/O Mapped
bit0
Page 29