NAND02GAH0LZC5E Micron Technology Inc, NAND02GAH0LZC5E Datasheet
NAND02GAH0LZC5E
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NAND02GAH0LZC5E Summary of contents
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NAND flash memories with MultiMediaCard™ interface Features Packaged NAND flash memory with MultiMediaCard interface 256 Mbytes and 1 Gbyte of formatted data storage eMMC/MultiMediaCard system specification, compliant with V4.3 Full backward compatibility with previous MultiMediaCard system specification Bus mode – ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 6.5 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N List of figures Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The NANDxxxxH0x is an embedded flash memory storage solution with MultiMediaCard ™ interface (eMMC communication media. The NANDxxxxH0x is fully compatible with MMC bus and hosts. The NANDxxxxH0x communications are made through an advanced 13-pin bus. The ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 2 Product specification 2.1 System performance Table 2. System performance System performance Multiple block read sequential Multiple block read 64-Kbyte chunk Multiple block write sequential Multiple block write 64-Kbyte chunk 1. Values given for an 8-bit bus ...
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Device physical description 3 Device physical description The NANDxxxxH0x contains a single chip controller and flash memory module, see Figure 1: Device block data to be written to and read from the flash memory module. The controller allows the host ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 3.1 Package connections Figure 2. LFBGA169 package connections (top view through package DAT2 ...
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Device physical description Figure 3. LFBGA153 package connections (top view through package DAT0 DAT1 DAT3 DAT4 DAT5 V CCI SSQ ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 3.2 Form factor The ball diameter, d, and the ball pitch, p, for the LFBGA169 and LFBGA153 packages are 0.30 mm (solder ball diameter 0.5 mm (ball pitch) Figure 4. Form factor V ...
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Memory array partitioning 4 Memory array partitioning The basic unit of data transfer to/from the device is one byte. All data transfer operations which require a block size always define block lengths as integer multiples of bytes. Some special functions ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 5 MultiMediaCard interface The signal/pin assignments are listed in 5.1 Signals description 5.1.1 Clock (CLK) The Clock input, CLK, is used to synchronize the memory to the host during command and data transfers. Each clock cycle gates ...
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MultiMediaCard interface 5.1.6 V input/output supply voltage CCQ V provides the power supply to the I/O pins and enables all outputs to be powered CCQ independently from V The input/output voltage (V range) or 2.7 V and 3.6 V (high ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 5.2 Bus topology The NANDxxxxH0x device supports the MMC protocol. For more details, refer to section 6.4 of the JEDEC Standard Specification No. JESD84-A43. The section 12 of the JEDEC Standard Specification contains a bus circuitry diagram ...
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MultiMediaCard interface Figure 6. Power-up Supply voltage (3) V CCmax ( (3) V CCmin (3) V CCQmax (3) V CCQmin Power-up 1. The initialization sequence is a contiguous stream of logic 1’s. Its length is either 1 ms, ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 5.5 Bus operating conditions Refer to section 12.6 of the JEDEC Standard Specification No. JESD84-A43. 5.6 Bus signal levels Refer to section 12.6 of the JEDEC Standard Specification No. JESD84-A43. 5.7 Bus timing Refer to section 12.7 ...
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High speed MultiMediaCard operation 6 High speed MultiMediaCard operation All communication between the host and the device is controlled by the host (master). The following section provides an overview of the identification and data transfer modes, commands, dependencies, various operation ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 6.6 Commands Refer to section 7.9 of the JEDEC Standard Specification No. JESD84-A43. 6.7 State transition Refer to section 7.10 and 7.12 of the JEDEC Standard Specification No. JESD84-A43. 6.8 Response Refer to section 7.11 of the ...
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Device registers 7 Device registers There are five different registers within the device interface: Operation conditions register (OCR) Card identification register (CID) Card specific data register (CSD) Relative card address register (RCA) DSR (driver stage register) Extended card specific data ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 7.2 Card identification (CID) register The CID register is 16-byte long and contains a unique card identification number used during the card identification procedure 128-bit wide register with the content as defined in Table ...
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Device registers Table 8. Card specific data register Name CSD structure MultiMediaCard protocol version Reserved Data read access-time-1 Data read access-time-2 in CLK cycles (NSAC*100) Max. data transfer rate Command classes Max. read data block length Partial blocks for read ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N Table 8. Card specific data register (continued) Name Permanent write protection Temporary write protection File format ECC code 2 R/W/E none 0 CRC Not used, always ‘1’ 7.4 Extended CSD register The extended CSD register defines the ...
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Device registers (1) Table 9. Extended CSD Name Sleep/awake timeout S_A_TIMEOUT (2) Reserved Sector count SEC_COUNT (2) Reserved Minimum write performance for 8 bit at MIN_PERF_W_8_52 52 MHz Minimum read performance for 8 bit at MIN_PERF_R_8_52 52 MHz Minimum write ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N (1) Table 9. Extended CSD Name Command set revision CMD_SET_REV (2) Reserved Power class POWER_CLASS (2) Reserved High speed interface HS_TIMING timing (2) Reserved Bus width mode BUS_WIDTH (2) Reserved Erased memory content ERASED_MEM_CONT (2) Reserved Boot ...
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Device registers 7.5 RCA (relative card address) register The writable 16-bit relative card address (RCA) register carries the device address assigned by the host during the device identification. This address is used for the addressed host-card communication after the device ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 8 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, ...
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Package mechanical Table 10. LFBGA169 1.4 mm 132+21+16 3R14 - 0.50 mm, mechanical data Symbol Typ 1.00 b 0.30 D 12.00 D1 6.50 ddd E 16.00 E1 6.50 E2 10.50 E3 12.50 E4 ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N Figure 9. LFBGA153 11 1.3 mm 132 + 21 3R14 - 0.50 mm, package outline E E1 BALL "A1" Drawing is not to scale Package mechanical ...
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Package mechanical Table 11. LFBGA153 11 1.3 mm 132 + 21 3R14 - 0.50 mm, mechanical data millimeters Symbol Typ A – A1 – A2 1.00 b 0.30 D 11.50 D1 6.50 E 13.00 E1 6.50 e ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 9 Ordering information Table 12. Ordering information scheme Example: Device type NAND flash memory Density 02G = 256 Mbytes 08G = 1 Gbyte Operating voltage 1 ...
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Revision history 10 Revision history Table 13. Document revision history Date 11-Nov-2008 22-Jan-2009 04-Mar-2009 32/33 NAND02GRH0L, NAND02GAH0L, NAND08GAH0N Revision 1 Initial release. Removed the 4-Gbit density and references to ECOPACK packages 2 throughout the document. LFBGA153 package replaced by LFBGA169. ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND ...