THNCF256MAA Toshiba, THNCF256MAA Datasheet - Page 14

• Manufacturer Part Number: THNCF256MAA
• Manufacturer: Toshiba
• Type: CompactFlashr

Specifications of THNCF256MAA

• Density: 256MByte
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 60C
• Package Type: Not Required
• Mounting: Socket
• Pin Count: 50
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.97/4.5V
• Operating Supply Voltage (max): 3.63/5.5V
• Programmable: Yes
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Task File register access specifications
Task File register access specifications
Task File register access specifications
Task File register access specifications
There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory
address area. Each case of Task File registers read and write operations is executed under the condition as
follows. That area can be accessed by Byte/World/Odd Byte modes, which are defined by PC card standard
specifications.
(1)
(1) I/O address map
(1)
(1)
Task File Register Read Access Mode (1)
Task File Register Read Access Mode (1)
Task File Register Read Access Mode (1)
Task File Register Read Access Mode (1)
Mode
Mode
Mode
Mode
Standby mode
Byte access(8-bit)
Word access(16-bit)
Odd byte access(8-bit)
Note: x: L or H
Task File Register Write Access Mode (1)
Task File Register Write Access Mode (1)
Task File Register Write Access Mode (1)
Task File Register Write Access Mode (1)
Mode
Mode
Mode
Mode
Standby mode
Byte access(8-bit)
Word access(16-bit)
Odd byte access(8-bit)
Note: x: L or H
Task File Register Access Timing Example (
Task File Register Access Timing Example (1 1 1 1 ) ) ) )
Task File Register Access Timing Example (
Task File Register Access Timing Example (
I/O address map
I/O address map
I/O address map
-CE2/-CE1
D0 to D15
A0 to A10
-IOWR
-IORD
-REG
- - - - REG
- - - - REG
REG
REG
REG
REG
REG
REG
L
L
L
L
L
L
L
L
x
x
read cycle
- - - - CE2
- - - - CE2
CE2
CE2
CE2
CE2
CE2
CE2
H
H
H
L
H
H
H
L
L
L
Dout
- - - - CE1
- - - - CE1
CE1
CE1
CE1
CE1
CE1
CE1
H
H
H
H
L
L
L
L
L
L
A0
A0 - - - - IORD
A0
A0 - - - - IORD
A0
A0
A0
A0
H
L
H
x
L
x
x
x
x
x
IORD
IORD - - - - IOWR
IORD
IORD - - - - IOWR
IORD
IORD
H
H
H
H
L
L
L
L
x
x
IOWR
IOWR
IOWR - - - - OE
IOWR
IOWR
IOWR - - - - OE
H
H
H
H
L
L
x
x
L
L
OE
OE
OE - - - - WE
OE
OE
OE - - - - WE
H
H
H
H
H
H
H
H
x
x
THNCFxxxMAA Series
WE
WE
WE D8 to D15
WE
WE
WE D8 to D15
write cycle
Preliminary version
H
H
H
H
H
H
H
H
x
x
D8 to D15
D8 to D15
D8 to D15
High-Z
High-Z
High-Z
odd byte
odd byte
D8 to D15
D8 to D15
D8 to D15
Don’t care
Don’t care
Don’t care
odd byte
odd byte
Din
2001-09-05 14/52
D0 to D7
D0 to D7
High-Z
D0 to D7
D0 to D7
Don’t care
even byte
odd byte
D0 to D7
D0 to D7
even byte
odd byte
even byte
High-Z
D0 to D7
D0 to D7
even byte
Don’t care