M25PX32-VMF6E NUMONYX, M25PX32-VMF6E Datasheet - Page 31
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M25PX32-VMF6E
Manufacturer Part Number
M25PX32-VMF6E
Description
Manufacturer
NUMONYX
Datasheet
1.M25PX32-VMF6E.pdf
(68 pages)
Specifications of M25PX32-VMF6E
Cell Type
NOR
Density
32Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC W
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
4M
Supply Current
12mA
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M25PX32-VMF6E
Manufacturer:
MICRON
Quantity:
20 000
6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (DQ0).
The instruction sequence is shown in
The Write Status Register (WRSR) instruction has no effect on b6, b1 and b0 of the Status
Register. b6 is always read as ‘0’.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is t
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in
the user to set and reset the Status Register Write Disable (SRWD) bit in accordance with
the Write Protect (W/V
Protect (W/V
The Write Status Register (WRSR) instruction is not executed once the hardware protected
mode (HPM) is entered.
Figure 13. Write Status Register (WRSR) instruction sequence
S
C
DQ0
DQ1
PP
) signal allow the device to be put in the hardware protected mode (HPM).
PP
Table
) signal. The Status Register Write Disable (SRWD) bit and Write
0
1
High Impedance
3. The Write Status Register (WRSR) instruction also allows
2
Instruction
3
4
Figure
5
6
13.
7
MSB
7
8
6
9 10 11 12 13 14 15
5
Register In
4
Status
3
2
1
0
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) is
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