CY7C4251-10JCT Cypress Semiconductor Corp, CY7C4251-10JCT Datasheet - Page 4
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CY7C4251-10JCT
Manufacturer Part Number
CY7C4251-10JCT
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C4251-10JCT.pdf
(20 pages)
Specifications of CY7C4251-10JCT
Configuration
Dual
Density
64Kb
Access Time (max)
8ns
Word Size
9b
Organization
8Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
PLCC
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
35mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4251-10JCT
Manufacturer:
CYPR
Quantity:
4 321
Table 1. Pin Definitions (continued)
Document #: 38-06016 Rev. *D
RCLK
EF
FF
PAE
PAF
RS
OE
Pin
Read Clock
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
Name
I/O
O
O
O
O
I
I
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable
flag-offset register.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High-Z (high-impedance) state.
Description
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Page 4 of 20
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