CY7C4231-15AC Cypress Semiconductor Corp, CY7C4231-15AC Datasheet - Page 9

• Manufacturer Part Number: CY7C4231-15AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4231-15AC

• Configuration: Dual
• Density: 16Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 2Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06016 Rev. *C
Switching Waveforms
Write Cycle Timing
REN1,REN2
Read Cycle Timing
Notes:
15. t
16. t
(if applicable)
REN1,REN2
between the rising edge of RCLK and the rising edge of WCLK is less than t
between the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
SKEW1
WEN2
Q
D
WCLK
WEN1
WEN1
WEN2
WCLK
RCLK
0
0
RCLK
–Q
–D
OE
EF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
FF
8
8
t
ENS
t
OLZ
t
SKEW1
t
ENH
[15]
t
t
CLKH
CLKH
t
t
t
WFF
A
REF
t
OE
t
t
CLK
CKL
t
SKEW1
NO OPERATION
[16]
t
DS
t
t
CLKL
CLKL
t
ENS
SKEW1
SKEW1
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
t
VALID DATA
DH
t
ENH
t
REF
CY7C4421/4201/4211/4221
t
WFF
t
OHZ
CY7C4231/4241/4251
NO OPERATION
NO OPERATION
Page 9 of 19
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