M38510/21002BJA QP SEMICONDUCTOR, M38510/21002BJA Datasheet - Page 9

• Manufacturer Part Number: M38510/21002BJA
• Manufacturer: QP SEMICONDUCTOR

Specifications of M38510/21002BJA

• Lead Free Status / RoHS Status: Not Compliant

table IVC and the following procedures shall be used for programming device types 02 and 04.
device type 05, and the following procedures shall be used for programming the device.
4.9
4.10 Programming procedures for circuit C, device type 05. The programming characteristics of table IVC,
i. If any bit does not verify as programmed, it shall be considered a programming reject.
a. Connect the device in the electrical configuration for programming. The waveforms on figure 5C, device
b. Terminate all device outputs with a 10 kΩ resistor to V
c. Address the PROM with the binary address of the selected word to be programmed. Raise V
d. After a t
e. After a t
f. After a t
g. Other bits in the same word may be programmed sequentially while the V
h. Repeat 4.9b through 4.9g for all other bits to be programmed.
i. To verify programming, after t
j. If any bit does not verify as programmed, it shall be considered a programming reject.
a. Connect the device in the electrical configuration for programming. The output pins shall be terminated
b. Disable the device by applying V
c. Apply V
d. Address the PROM with the binary address of the selected word to be programmed and reset T
e. After a delay of TD
f. After a delay of TD
g. After a delay of TD
Programming procedures for circuit C, device types 02 and 04. The programming characteristics of
types 02 and 04, and the programming characteristics of table IVC, device types 02 and 04, shall apply
to these procedures.
output at a time.
cause the output to go to a high-level logic in the verify mode.)
applying V
on figure 5C.
The programmed output should remain in the “1” state. Again, lower V
programmed output remains in the “1” state.
with a 10 kΩ resistor to GND and bypass VCC to GND with a 0.01 µF capacitor. The waveforms on
figure 5C, device type 05, and the programming characteristics of table IVC, device type 05, shall apply
to these procedures.
compatible.
Address inputs are TTL compatible.
and wait TD
IL
D
D
D
delay (10 µs), apply only one V
delay (10 µs), pulse CE
delay (10 µs), remove the V
to all other pins.
OUT
4
.
pulses to each output to be programmed allowing a delay to t
1
2
3
, raise the V
, raise the corresponding output pin to V
, lower CE
D
2
(10 µs) delay, lower V
CC
to V
IH
1
pin to V
to CE
input to logic “0” for a duration of t
IL
OUT
MIL-M-38510/210E
for a duration of T
pulse from the programmed output. (Programming a fuse will
OUT
2
CCP
input and V
pulse to the output to be programmed. Program one
.
9
CC
CC
IL
to V
P
. Apply V
to CE
and simultaneously lower the output to V
OPF
CCH
1
.
. The chip enable pins are TTL
and apply a logic “0” level to CE
IH
to CE
P
.
CC
CC
to V
1
.
D
input is at the V
between pulses as shown
CCL
and verify that the
CCP
CC
P
level by
to V
1
= 5 µs.
input.
IL
CCP
.