MT4LC4M16R6TG-5SIT Micron Technology Inc, MT4LC4M16R6TG-5SIT Datasheet
MT4LC4M16R6TG-5SIT
Specifications of MT4LC4M16R6TG-5SIT
Related parts for MT4LC4M16R6TG-5SIT
MT4LC4M16R6TG-5SIT Summary of contents
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... MARKING † A12 for N3 version, NC for R6 version. N3 None S* Configuration Refresh None Row Address Column Addressing 4 MEG x 16 EDO DRAM PART NUMBERS PART NUMBER MT4LC4M16R6TG-x MT4LC4M16R6TG MT4LC4M16N3TG-x AA CAC CAS MT4LC4M16N3TG-x S 25ns 13ns 8ns 30ns 15ns 10ns x = speed 1 4 MEG x 16 EDO DRAM www ...
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... BUFFER(9) REFRESH CONTROLLER A0- A12 REFRESH COUNTER ROW- 13 ADDRESS BUFFERS (13) NO. 1 CLOCK RAS# GENERATOR 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 FUNCTIONAL BLOCK DIAGRAM MT4LC4M16R6 (12 row addresses) CAS# DATA-IN BUFFER 4,096 FUNCTIONAL BLOCK DIAGRAM MT4LC4M16N3 (13 row addresses) CAS# DATA-IN BUFFER 9 13 ...
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... GENERAL DESCRIPTION The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The device is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns on the MT4LC4M16R6 or 8,192 rows by 512 columns on the MT4LC4M16N3 ...
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... CAS#. If CAS# went HIGH and OE# was LOW (active), the output buffers would be disabled. The 64Mb EDO DRAM offers an accelerated page mode cycle by elimi- nating output disable from CAS# HIGH. This option is called EDO, and it allows CAS# precharge time ( occur without the output data going invalid (see READ and EDO-PAGE-MODE READ waveforms) ...
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... COLUMN ( IOH DQ OPEN V IOL Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 COLUMN (B) VALID DATA (A) VALID DATA (A) VALID DATA ( OES t OE The DQs go back to t Low-Z if OES is met. Figure 3 OE# Control of DQs COLUMN (B) VALID DATA (A) t WHZ t WPZ The DQs go to High-Z if WE# falls and, if will remain High-Z until CAS# goes LOW with WE# HIGH (i ...
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... DRAM. The refresh requirements are met by refreshing all rows in the 4 Meg x 16 DRAM array at least once every 64ms (8,192 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 rows for N3 or 4,096 rows for R6). The recommended ...
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... Any output at V OUT OUT DQ is disabled and in High-Z state 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional ...
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... REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with RAS# ³ and CAS# held LOW; WE 0.2V or 0.2V (D may be left open Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 = +3.3V ±0.3V) CC £ 0.2V [MIN [MIN [MIN [MIN]) - 0.2V ...
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... OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 = +3.3V ±0.3V SYMBOL MIN ...
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... WRITE command hold time (referenced to RAS#) WE# command setup time WE# to outputs in High-Z WRITE command pulse width WE# pulse widths to disable outputs WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 = +3.3V ±0.3V SYMBOL MIN MAX ...
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... AA ( RAC and applied). With or without the AA, RAC, and CAC must always be met. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 . 16. Either = +3.3V cycle 17. achieves the open circuit condition and is not referenced 18. ...
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... Last falling CASx# edge to first rising CASx# edge. 32. Last rising CASx# edge to first falling CASx# edge. 33. Last rising CASx# edge to next cycle’s last rising CASx# edge. 34. Last CASx LOW. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 35. V overshoot: V (MAX width ≤ ...
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... CLCH 5 t CLZ 0 t CRP 5 t CSH NOTE: 1. OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 READ CYCLE RAS t CSH t RSH t RCD t CAS RAD t RAH t ASC t CAH t ACH COLUMN t RCS t AA ...
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... CAH 8 t CAS 8 10,000 t CLCH 5 t CRP 5 t CSH 38 t CWL Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 EARLY WRITE CYCLE RAS t CSH t RSH t RCD t CAS RAD t RAH t ASC t CAH COLUMN t CWL t RWL t WCR t WCS t WCH VALID DATA -6 MAX ...
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... CLCH 5 t CLZ 0 t CRP 5 t CSH 38 t CWD 28 t CWL Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 READ-WRITE CYCLE t RWC t RAS t CSH t RSH t RCD t CAS RAD t ASC t CAH t RAH COLUMN t RWD t RCS t CWD t AWD RAC t CAC t CLZ OPEN ...
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... CLCH 5 t CLZ 0 t COH CPA 28 t CRP 5 t CSH Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 EDO-PAGE-MODE READ CYCLE t RASP RCD t CAS ACH t ACH t ASC t CAH t ASC COLUMN COLUMN t RCS RAC t CAC t CLZ VALID DATA OES -6 MAX UNITS ...
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... ASR 0 t CAH 8 t CAS 8 10,000 t CLCH CRP 5 t CSH 38 t CWL Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 t RASP RCD t CAS ACH t ASC t CAH t ASC COLUMN COLUMN t CWL t WCH t WCS WCR VALID DATA VALID DATA -6 MAX UNITS SYMBOL ...
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... CPA 28 t CRP 5 t CSH 38 t CWD 28 t CWL NOTE for LATE WRITE cycles only. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 EDO-PAGE-MODE READ-WRITE CYCLE t RASP t CSH t RCD CAS t ASC t CAH t ASC COLUMN COLUMN t RWD t RCS t CWL AWD t CWD t AA ...
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... CAH 8 t CAS 8 10,000 t COH CPA 28 t CRP 5 t CSH Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 (Pseudo READ-MODIFY-WRITE) t RASP t CSH CAS CAS ASC t CAH t ASC t CAH COLUMN (A) COLUMN (B) t RCS CPA t RAC t CAC t CAC t COH VALID DATA ( MAX ...
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... ASC 0 t ASR 0 t CAC 13 t CAH 8 t CAS 8 10,000 t CLZ CRP 5 t CSH 38 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 READ CYCLE (with WE#-controlled disable) t RCD RAD t RAH t ASC ROW COLUMN t RCS OPEN -6 MAX UNITS SYMBOL RAC ...
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... CRP 5 t CSR 5 t RAH 7 NOTE: 1. End of first CBR REFRESH cycle. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) t RAS t RAH ROW OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE RAS ...
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... CHR 8 t CLZ 0 t CRP NOTE HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 HIDDEN REFRESH CYCLE (WE# = HIGH; OE# = LOW RAS RCD t RSH RAD t RAH t ASC t CAH ...
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... RASS 100 t NOTE: 1. Once RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode Once RPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 SELF REFRESH CYCLE (Addresses and OE# = DON’ ...
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... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 50-PIN PLASTIC TSOP (400 mil) ...