MT41J256M4HX-187E:D Micron Technology Inc, MT41J256M4HX-187E:D Datasheet - Page 132
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MT41J256M4HX-187E:D
Manufacturer Part Number
MT41J256M4HX-187E:D
Description
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Datasheet
1.MT41J256M4HX-187ED.pdf
(208 pages)
Specifications of MT41J256M4HX-187E:D
Organization
256Mx4
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
190mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
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Figure 53: Mode Register 0 (MR0) Definitions
Burst Type
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
M15
0
0
1
1
M14
0
1
0
1
Mode register 0 (MR0)
Mode register 1 (MR1)
Mode register 2 (MR2)
Mode register 3 (MR3)
Mode Register
Note:
starting location within the block. The programmed burst length applies to both READ
and WRITE bursts.
Accesses within a given burst may be programmed to either a sequential or an inter-
leaved order. The burst type is selected via MR0[3] (see Figure 53 (page 132)). The
ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst
access modes. Full interleave address ordering is supported for READs, while WRITEs
are restricted to nibble (BC4) or word (BL8) boundaries.
1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to 0.
BA2
0 1
16
M11
M12
15
BA1
0
0
0
0
1
1
1
1
0
0
1
M10
DLL off (slow exit)
0
DLL on (fast exit)
BA0
0
0
1
1
0
0
1
1
14
Precharge PD
M9
0 1
13
0
1
0
1
0
1
0
1
A13
PD
12
Write Recovery
A12 A11
Reserved
Reserved
11
10
12
5
6
7
8
WR
10
A10
M8
0
1
9
A9
DLL Reset
DLL
132
8
A8
Yes
No
M6
0
0
0
0
1
1
1
1
0 1
7
A7 A6 A5 A4 A3
M5
0
0
1
1
0
0
1
1
CAS# latency BT
6
M4
0
1
0
1
0
1
0
1
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
CAS Latency
4
Reserved
10
11
3
5
6
7
8
9
1Gb: x4, x8, x16 DDR3 SDRAM
2
A2 A1 A0
1
0
M3
0
1
M1
0
0
1
1
Address bus
Mode register 0 (MR0)
Mode Register 0 (MR0)
Sequential (nibble)
M0
READ Burst Type
0
1
0
1
Interleaved
4 or 8 (on-the-fly via A12)
© 2006 Micron Technology, Inc. All rights reserved.
Fixed BC4 (chop)
Burst Length
Fixed BL8
Reserved
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