W981216AH-75G Winbond, W981216AH-75G Datasheet

Page 1

... Package: TSOP II 54 pin, 400 mil - 0.80 General Description W981216AH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 2M words x 4 banks x 16 bits. Using pipelined architecture and 0.20um process technology, W981216AH delivers a data bandwidth 266M bytes per second (-75). To fully comply to the personal computer industrial standard, W981216AH is sorted into two speed grades: -75 and -8H. The -75 is compliant to the PC133/CL3 specification, the – ...

Page 2

... MODE REGISTER A0 ADDRESS BUFFER A9 A11 BS0 BS1 REFRESH COLUMN COUNTER COUNTER Revision 1 bit x 4 Banks SDRAM COLUMN DECODER CELL ARRAY BANK #0 SENSE AMPLIFIER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 4096 * 512 * 16 COLUMN DECODER ...

Page 3

... Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Separated power from V , used for output buffers to improve CC noise. Separated ground from V , used for output buffers to improve SS noise. No connection - 3 - W981216AH Publication Release Date: March, 1999 ...

Page 4

... Pin Assignment (Top View) Revision 1 bit x 4 Banks SDRAM DQ0 DQ1 4 DQ2 DQ3 7 DQ4 DQ5 10 DQ6 DQ7 LDQM CAS 17 RAS BS0 20 BS1 21 A10/ DQ15 DQ14 51 DQ13 DQ12 48 DQ11 DQ10 45 44 DQ9 DQ8 UDQM 39 CLK 38 37 CKE NC 36 A11 Publication Release Date: March, 1999 ...

Page 5

... Note: These parameters are periodically sampled and not 100% tested. Revision 1 bit x 4 Banks SDRAM ITEM RATING -0.3~V +0.3 CC -0.3~4.6 0~70 -55~150 260 1 50 MIN TYP 3.0 3.3 3.0 3.3 2.0 - -0.3 - PARAMETER - 5 - W981216AH UNIT NOTES °C 1 °C 1 ° °C MAX UNIT NOTES 3 3.6 ...

Page 6

... CL*=2 10 CL*=3 7.5 CL*=2 10 1000 CL*=3 7.5 1000 2.5 2.5 CL*=2 6 CL*=3 5.4 2.7 2.7 7 7.5 0.5 10 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0 Publication Release Date: March, 1999 - 6 - W981216AH -8H (PC100) UNIT MIN MAX 68 48 100000 cycle 1000 8 1000 0 ...

Page 7

... CC2 (Power Down mode CC2P I IH CC2S (Power Down mode CC2PS I IH CC3 (Power Down mode CC3P I CC4 I CC5 I CC6 SYMBOL I I( W981216AH -75 (PC133) -8H (PC100) MIN. MAX. MIN. MAX 120 110 190 180 2 2 MIN. MAX. UNIT -5 5 µ µA 2 ...

Page 8

... HZ Revision 1 bit x 4 Banks SDRAM SS 3.3 V 1.2K output 0.87K and W981216AH 1.4V/1.4V See diagram B below 2.4V/0.4V 2ns 1.4V 1 ohms ohms 50pF AC TEST LOAD (B) Publication Release Date: March, 1999 ...

Page 9

... Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. Revision 1 bit x 4 Banks SDRAM Table 1 Truth Table ( note (1) , (2) ) CKEn-1 CKEn DQM BS0 W981216AH A11, A10 CS RA CAS A9 ...

Page 10

... V CC RCD (max). RAS delay. WE pin voltage level defines whether the access cycle is a read operation RCD - 10 - W981216AH supplies. After power up, CC has elapsed. Please refer to the next page for RSC ). Once a bank has been activated it must be ). The minimum RC ...

Page 11

... The data DQs high impedance state after a delay which is equal to the CAS Latency in a burst read cycle interrupted by Burst Stop Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. Revision 1 bit x 4 Banks SDRAM Publication Release Date: March, 1999 - 11 - ...

Page 12

... A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode DATA Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Revision 1 bit x 4 Banks SDRAM n BL= 2 (disturb address is A0 BL= 4 (disturb addresses are A0 and A1 BL= 8 (disturb addresses are A0, A1 and A2 Access Address ...

Page 13

... Banks SDRAM . The bank undergoing auto-precharge can not be reactivated until t DPL = DAL DPL ). the device. REF - 13 - W981216AH ) has been satisfied. Issue of Auto-Precharge RP ). When using the Auto-precharge Command, the RP RAS Publication Release Date: March, 1999 and t are DPL RP (min). (min) + ...

Page 14

... No Operation Command The No Operation Command should be used in cases when the SDRAM idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle ...

Page 15

... Command Input Timing V IH CLK RAS CAS WE A0-A11 BS0 CKS CKH CKE Revision 1 bit x 4 Banks SDRAM t t CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKH CKS - 15 - W981216AH CMH t t CKS CKH Publication Release Date: March, 1999 t CMS ...

Page 16

... Read Timing CLK CS RAS CAS WE A0-A11 BS0 Read Command Revision 1 bit x 4 Banks SDRAM Read CAS Latency Data-Out - 16 - W981216AH Valid Valid Data-Out Burst Length Publication Release Date: March, 1999 ...

Page 17

... DS DH Valid Data- CKS CKH CKS Valid Data- CMS CMH CMS Valid Valid Data-Out Data-Out CKS CKH CKS Valid Data-Out - 17 - W981216AH Valid Valid Data-in Data- Valid Valid Data-in Data- Valid Data-Out OPEN Valid Valid Data-Out Data-Out Publication Release Date: March, 1999 ...

Page 18

... Banks SDRAM t RSC A0 A0 Burst Length Sequential Reserved Full Page Addressing Mode Sequential Interleave CAS Latency Reserved Reserved Single Write Mode A0 0 Burst read and Burst write Burst read and single write A0 Publication Release Date: March, 1999 - 18 - W981216AH next command Interleave Reserved A0 ...

Page 19

... RAS t t RCD RCD RBb RAc CBx RBb RAc t AC bx1 aw0 aw1 aw2 aw3 bx0 t RRD Active Precharge Active Read - 19 - W981216AH RAS RAS t RCD RBd CAy RBd CBz t AC bx3 cy2 bx2 cy1 cy3 cy0 t t RRD RRD Precharge Read ...

Page 20

... Banks SDRAM (CLK = 100 MHz RAS t RCD t RCD RAc CBx RAc aw0 aw1 aw2 aw3 bx0 t RRD AP* Active Read - 20 - W981216AH RAS RAS t RCD RBd CAy CBz RBd t AC bx1 bx2 bx3 cy0 cy1 cy2 cy3 t t RRD RRD Read ...

Page 21

... CLK CS RAS CAS WE BS0 BS1 t RCD A10 RAa A0-A9 RAa CAx A11 DQM CKE DQ t RRD Read Active Bank #0 Bank #1 Precharge Bank #2 Idle Bank #3 Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz RAS RCD RBb RBb CBy ax0 ax1 ax2 ax3 ...

Page 22

... CLK CS RAS CAS WE BS0 BS1 t RCD A10 RAa A0-A9 CAx RAa DQM CKE DQ t RRD Read Bank #0 Active Bank #1 Bank #2 Idle Bank #3 Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz RAS t RCD RBb RBb CBy t CAC ax3 ax4 ax0 ax1 ax2 ...

Page 23

... Banks SDRAM (CLK = 100 MHz RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 t RRD Precharge Active Write - 23 - W981216AH RAS t RAS t RCD RAc RAc CAz by3 by4 by5 by6 by7 CZ0 Active Write Publication Release Date: March, 1999 ...

Page 24

... BS0 BS1 t RCD RAa A10 A0-A9, CAx RAa A11 DQM CKE ax0 ax1 DQ t RRD Active Write Bank #0 Bank #1 Bank #2 Idle Bank #3 Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz RAS t RCD RBb CBy RBb ax4 by2 ax5 ax6 ax7 by0 ...

Page 25

... CCD CCD t RAS t RAS t RCD CBx CAy CAm bx0 Ay0 a2 bx1 Read Read Read * AP is the internal precharge start timing - 25 - W981216AH CCD t RP CBz am1 am2 bz0 bz1 bz2 Ay1 Ay2 am0 Precharge Read AP* Publication Release Date: March, 1999 21 22 ...

Page 26

... A11 DQM CKE DQ Bank #0 Active Read Bank #1 Bank #2 Idle Bank #3 Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz RAS t AC ax5 ax0 ax1 ax3 ax2 ax4 W981216AH CAy t WR ay1 ay0 ay2 ay4 ay3 Write Precharge Publication Release Date: March, 1999 ...

Page 27

... Bank #1 Bank #2 Idle Bank #3 Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz RAb RAb t AC aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing - 27 - W981216AH RAS t RCD CAx t AC bx0 bx1 Read AP* Publication Release Date: March, 1999 bx2 bx3 ...

Page 28

... Active Bank #0 Write Bank #1 Bank #2 Idle Bank #3 Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz RCD RAb RAb CAx bx0 aw3 Active Write AP the internal precharge start timing - 28 - W981216AH RAS RP bx1 bx3 bx2 AP* Publication Release Date: March, 1999 RAc RAc Active ...

Page 29

... AutoRefresh cycle CLK RAS CAS WE BS0,1 A10 A0-A9, A11 DQM CKE DQ All Banks Auto Prechage Refresh Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz W981216AH Auto Refresh (Arbitrary Cycle) Publication Release Date: March, 1999 22 23 ...

Page 30

... CLK RAS CAS WE BS0,1 A10 A0-A9, A11 DQM CKE t CKS DQ All Banks Self Refresh Precharge Entry Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz CKS t SB Self Refresh Cycle - 30 - W981216AH CKS Operation Cycle Publication Release Date: March, 1999 Arbitrary Cycle ...

Page 31

... Read Active Bank #0 Bank #1 Bank #2 Idle Bank #3 Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz CBw t AC av0 av1 av3 aw0 av2 Single Write - 31 - W981216AH CBz CBx CBy t AC ax0 ay0 az1 az2 az0 Read Publication Release Date: March, 1999 az3 Q ...

Page 32

... When CKE goes high, command input must be No operation at next CLK rising edge. Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz CAa t CKS ax0 ax1 ax2 ax3 Precharge - 32 - W981216AH RAa RAa CKS NOPActive Precharge Standby Power Down mode Publication Release Date: March, 1999 22 23 ...

Page 33

... Revision 1 bit x 4 Banks SDRAM Act Act Act Act Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. (min). RAS - 33 - W981216AH Act Act AP Act Publication Release Date: March, 1999 ...

Page 34

... Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS(min). Revision 1 bit x 4 Banks SDRAM Act Act W981216AH Act Q3 AP Act Publication Release Date: March, 1999 ...

Page 35

... Revision 1 bit x 4 Banks SDRAM Act Act Act Act represents the Write with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command W981216AH Act AP Act Act Publication Release Date: March, 1999 11 Act ...

Page 36

... Revision 1 bit x 4 Banks SDRAM Act t RP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command W981216AH Act Publication Release Date: March, 1999 10 11 Act ...

Page 37

... DQM DQ (3) CAS Latency Command DQM Command DQM DQ Note ) The Output data must be masked by DQM to avoid I/O conflict Revision 1 bit x 4 Banks SDRAM Read Write Read Write Read Write Read Write Read Write Read Write W981216AH Publication Release Date: March, 1999 11 ...

Page 38

... Command Write DQM D0 DQ (2) CAS Latency Command Write DQM Command Write DQM D0 DQ (3) CAS Latency=4 Write ( a ) Command DQM Command Write DQM D0 DQ Revision 1 bit x 4 Banks SDRAM Read Q0 Q1 Read D1 Q0 Read Q0 Read D1 Read Read W981216AH Publication Release Date: March, 1999 11 ...

Page 39

... Read cycle ( a ) CAS latency =2 Read Command )CAS latency = 3 Read Command )CAS latency = 4 Read Command DQ (2) Write cycle Write Command BST Note ) Revision 1 bit x 4 Banks SDRAM BST BST BST BST represents the Burst stop command - 39 - W981216AH Publication Release Date: March, 1999 ...

Page 40

... CAS latency =2 Write Commad DQM )CAS latency = 3 Write Commad DQM )CAS latency = 4 Write Commad DQM D0 DQ Note ) Revision 1 bit x 4 Banks SDRAM PRCG PRCG PRCG Q0 Q1 PRCG PRCG PRCG PRCG represents the Precharge command - 40 - W981216AH Publication Release Date: March, 1999 11 ...

Page 41

... CKE/DQM Input timing ( Write cycle ) 1 CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM D1 DQ Revision 1 bit x 4 Banks SDRAM DQM MASK ( DQM MASK ( CKE MASK ( CKE MASK CKE MASK ...

Page 42

... CKE/DQM Input timing ( Read cycle ) 1 CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM Q1 DQ Revision 1 bit x 4 Banks SDRAM Open Open Open Publication Release Date: March, 1999 ...

Page 43

... Self Refresh mode NOP Represents the No-Operation command Command Represents one command Revision 1 bit x 4 Banks SDRAM (min (min)+t (min) CKS CK NOP Command Input Buffer Enable (min (min)+t (min) CKS CK Command Input Buffer Enable - 43 - W981216AH Publication Release Date: March, 1999 ...

Page 44

... Package Dimension 54L TSOP (II) mil Controlling Dimension : Millimeters SYMBOL Revision 1 bit x 4 Banks SDRAM SEATING PLANE DIMENSION DIMENSION (MM) (INCH) MIN. NOM. MAX. MIN. 1.20 0.15 0.05 0.10 0.002 0.004 1.00 0.039 0.24 0.32 0.40 0.009 0.012 0.15 0.006 22.12 22.22 22.62 ...