K4S281632IUI75 Samsung Semiconductor, K4S281632IUI75 Datasheet
K4S281632IUI75
Specifications of K4S281632IUI75
Related parts for K4S281632IUI75
K4S281632IUI75 Summary of contents
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... K4S280432I K4S280832I K4S281632I 128Mb I-die SDRAM Specification INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4S280432I K4S280832I K4S281632I Revision History Revision Month Year 1.0 October 2005 1.1 May 2006 - Final spec release. - Added 5ns speed bin for x16 Synchronous DRAM History Rev. 1.1 May 2006 ...
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... K4S280432I K4S280832I K4S281632I 8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & Burst length ( & ...
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... TSOP(II) Package Dimension Synchronous DRAM 0~8°C 0.25 TYP 0.010 +0.075 0.125 -0.035 +0.003 0.005 -0.001 1.00 1.20 ± 0.05 ± 0.10 MAX 0.039 0.047 ± ...
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... CLK CKE * Samsung Electronics reserves the right to change products or specification without notice. Data Input Register Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register CS RAS CAS Synchronous DRAM LWCBR LDQM L(U)DQM Rev. 1.1 May 2006 LWE LDQM DQi ...
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... Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device Synchronous DRAM x8 x16 DQ7 DQ15 V V SSQ SSQ N ...
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... A Min Typ , V 3.0 3.3 DDQ V 2 =1.4V ± 200 mV) = 23° 1MHz, V REF Symbol C CLK ADD ~ OUT Synchronous DRAM Value Unit -1.0 ~ 4.6 V -1.0 ~ 4.6 V °C -55 ~ +150 Max Unit Note -2mA OH 0 2mA Min Max Unit 2.5 3.5 2.5 3 ...
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... Input signals are changed one time during 20ns CKE ≥ V (min), CLK ≤ ∞ (max Input signals are stable Page burst ≥ (min CKE ≤ 0. DDQ SSQ Synchronous DRAM Version 110 200 800 Rev. 1.1 May 2006 Unit Note ...
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... CLK ≤ ∞ (max Input signals are stable Page burst 4Banks Activated t = 2CLKs CCD ≥ (min CKE ≤ 0. DDQ SSQ Synchronous DRAM Version 140 130 100 160 150 140 230 220 200 2 L 800 Rev. 1.1 May 2006 Unit Note mA ...
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... RCD t (min (min) 40 RAS t (max) RAS t (min (min) RDL t (min) 2 CLK + tRP DAL t (min) CDL t (min) BDL t (min) CCD CAS latency=3 CAS latency Synchronous DRAM Unit Vtt = 1.4V 50Ω 50Ω 50pF (Fig output load circuit Version Unit 60 (x16 100 CLK - 1 CLK ...
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... Measure in linear 1.37 region : 1.2V ~ 1.8V Measure in linear 1.30 region : 1.2V ~ 1.8V Measure in linear 2.8 region : 1.2V ~ 1.8V Measure in linear 2.0 region : 1.2V ~ 1.8V , use these values to design to use these values to design to Synchronous DRAM 75 Unit Max Min Max 7.5 1000 1000 5 ...
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... Pull-down 250 200MHz 166MHz 133MHz 200 Max I (mA) 0.0 150 70.2 107.5 133.8 100 151.2 187.7 194.4 50 202.5 208.6 212.0 0 219.6 0 222 Synchronous DRAM 200MHz/166MHz /133MHz Pull-up 0.5 1 1.5 2 2.5 3 Voltage I Min (200MHz/166MHz/133MHz Max (200MHz/166MHz/133MHz) OH 0.5 1 1.5 2 2.5 3 Voltage I Min (200MHz/166MHz/133MHz ...
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... Synchronous DRAM Minimum V clamp current DD (Referenced Voltage I (mA) Minimum V clamp current -10 -20 -30 -40 -50 -60 Voltage ...
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... MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...