W9825G6DH75I Winbond, W9825G6DH75I Datasheet - Page 11
![no-image](/images/manufacturer_photos/0/7/712/winbond_sml.jpg)
W9825G6DH75I
Manufacturer Part Number
W9825G6DH75I
Description
Manufacturer
Winbond
Type
SDRAMr
Datasheet
1.W9825G6DH75I.pdf
(44 pages)
Specifications of W9825G6DH75I
Organization
16Mx16
Density
256Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Supplier Unconfirmed
W9825G6DH
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (t
) of the
REF
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on t
. The input buffers need to be
CK
enabled with CKE held high for a period equal to t
(min) + t
(min).
CKS
CK
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS , CAS and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS , CAS and WE signals become don't
cares.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
Publication Release Date:Apr. 24, 2008
- 11 -
Revision A12