MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 119

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

CAS Write Latency (CWL)
Figure 56: CAS Write Latency
AUTO SELF REFRESH (ASR)
SELF REFRESH TEMPERATURE (SRT)
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
BC4
DQS, DQS#
Command
CK#
DQ
CK
ACTIVE n
T0
WRITE n
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the
internal write to the latching of the first data in. CWL must be correctly set to the corre-
sponding operating clock frequency (see Figure 55 on page 118). The overall WRITE
latency (WL) is equal to CWL + AL (Figure 53 on page 115), as shown in Figure 56.
Mode register MR2[6] is used to disable/enable the ASR function.
When ASR is disabled, the self refresh mode’s refresh rate is assumed to be at the normal
85°C limit (sometimes referred to as 1X refresh rate). In the disabled mode, ASR requires
the user to ensure the DRAM never exceeds a T
user enables the SRT feature listed below when the T
Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1X to
2X when the case temperature exceeds 85°C. This enables the user to operate the DRAM
beyond the standard 85°C limit up to the optional extended temperature range of 95°C
while in self refresh mode.
The standard self refresh current test specifies test conditions to normal case tempera-
ture (85°C) only, meaning if ASR is enabled, the standard self refresh current specifica-
tions do not apply (see “Extended Temperature Usage” on page 152).
Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (sometimes
referred to as 1X refresh rate). In the disabled mode, SRT requires the user to ensure the
DRAM never exceeds a T
When SRT is enabled, the DRAM self refresh is changed internally from 1X to 2X, regard-
less of the case temperature. This enables the user to operate the DRAM beyond the
standard 85°C limit up to the optional extended temperature range of 95°C while in self
refresh mode. The standard self refresh current test specifies test conditions to normal
case temperature (85°C) only, meaning if SRT is enabled, the standard self refresh
current specifications do not apply (see “Extended Temperature Usage” on page 152).
T1
t RCD (MIN)
NOP
AL = 5
T2
WL = AL + CWL = 11
C
of 85°C while in self refresh mode unless the user enables ASR.
NOP
T6
119
CWL = 6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T11
NOP
Indicates A Break in
Time Scale
C
of 85°C while in self refresh unless the
2Gb: x4, x8, x16 DDR3 SDRAM
C
NOP
T12
DI
is between 85°C and 95°C.
n
n + 1
DI
©2006 Micron Technology, Inc. All rights reserved.
Transitioning Data
n + 2
NOP
T13
DI
Operations
n + 3
DI
Don’t Care
NOP
T14