MT47H64M16HR-3:H Micron Technology Inc, MT47H64M16HR-3:H Datasheet - Page 109
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MT47H64M16HR-3:H
Manufacturer Part Number
MT47H64M16HR-3:H
Description
IC DDR2 SDRAM 1GBIT 84FBGA
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Series
-r
Datasheet
1.MT47H64M16HR-3H.pdf
(134 pages)
Specifications of MT47H64M16HR-3:H
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
450ps
Maximum Clock Rate
667MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
135mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (64M x 16)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
84-TFBGA
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT47H64M16HR-3:H
Manufacturer:
MICRON
Quantity:
11 200
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MT47H64M16HR-3:H
Manufacturer:
MICRON
Quantity:
20 000
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Part Number:
MT47H64M16HR-3:H
Manufacturer:
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Company:
Part Number:
MT47H64M16HR-3:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT47H64M16HR-3:H
Manufacturer:
MICRON
Quantity:
20 000
Company:
Part Number:
MT47H64M16HR-3:H TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 61: WRITE-to-READ
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
Command
DQS, DQS#
DQS, DQS#
DQS, DQS#
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
Address
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE
Bank a,
Col b
T0
WL - t DQSS
Notes:
WL ± t DQSS
WL + t DQSS
NOP
T1
1.
2. Subsequent rising DQS signals must align to the clock within
3. DI b = data-in for column b; DO n = data-out from column n.
4. BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. One subsequent element of data-in is applied in the programmed order following DI b.
6.
7. A10 is LOW with the WRITE command (auto precharge is disabled).
8. The number of clock cycles required to meet
t
quired between module ranks.
t
greater.
DI
b
WTR is required for any READ following a WRITE to the same device, but it is not re-
WTR is referenced from the first positive CK edge after the last data-in pair.
NOP
T2
DI
b
DI
b
T2n
2
NOP
T3
2
2
T3n
NOP
T4
109
t WTR 1
T5
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Bank a,
1Gb: x4, x8, x16 DDR2 SDRAM
READ
T6
Col n
t
WTR is either 2 or
CL = 3
CL = 3
CL = 3
T7
NOP
Transitioning Data
© 2004 Micron Technology, Inc. All rights reserved.
t
DQSS.
t
WTR/
T8
NOP
t
CK, whichever is
T9
NOP
Don’t Care
WRITE
DI
DI
DI
T9n