PF38F1030W0YBQF Micron Technology Inc, PF38F1030W0YBQF Datasheet - Page 14

• Manufacturer Part Number: PF38F1030W0YBQF
• Manufacturer: Micron Technology Inc

Specifications of PF38F1030W0YBQF

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

4.2
Table 4:
Datasheet
14
Address and Data Signals, Non-Mux
A[MAX:0]
DQ[15:0]
Address and Data Signals, AD-Mux
DQ[15:0]
Control Signals
ADV#
F[3:1]-
CE#
CLK
F[2:1]-
OE#
Symbol
Input /
Input /
Output
Output
Type
Input
Input
Input
Input
Input
Signal Descriptions (Sheet 1 of 3)
Signal Descriptions
ADDRESS: Global device signals.
Shared address inputs for all memory die during Read and Write operations.
Note:
DATA INPUT/OUTPUTS: Global device signals.
Inputs data and commands during Write cycles, outputs data during Read cycles. Data signals are
High-Z when the device is deselected or its output is disabled.
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux I/O flash signals.
During AD-Mux Read cycles, DQ[15:0] are used to input the lower address followed by read-data
output. During AD-Mux Write cycles, DQ[15:0] are used to input the lower address followed by
commands or data.
ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input.
During a synchronous read operation, the address is latched on the rising edge of
ADV# or on the next valid CLK edge with ADV# low, whichever occurs first.
Note:
FLASH CHIP ENABLE: Flash-specific signal; low-true input.
When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the
associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT outputs
are placed in a High-Z state.
CLOCK: Flash- and Synchronous PSRAM-specific input signal.
CLK synchronizes the flash and/or synchronous PSRAM with the system clock during synchronous
operations.
FLASH OUTPUT ENABLE: Flash-specific signal; low-true input.
When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE# disables
the output drivers of the selected flash die and places the output drivers in High-Z.
• 128-Mbit: AMAX = A22
• 64-Mbit: AMAX = A21
• 32-Mbit: AMAX = A20
• 16-Mbit: AMAX = A19
• A0 is the lowest-order word address.
• Unused address inputs should be treated as RFU.
• DQ[15:0] are High-Z when the device is deselected or its output is disabled.
• DQ[15:0] is only used with AD-Mux I/O flash device.
• In an asynchronous flash read operation, the address is latched on the rising edge of ADV#, or
• During a synchronous flash Read operation, the address is latched on the rising edge of ADV#
• During synchronous PSRAM read and synchronous write modes, the address is either latched
• F1-CE# is dedicated to flash die #1.
• F[3:2]-CE# are dedicated to flash die #3 through #2, respectively, if present. Otherwise, any
• F2-OE# common to all other flash dies, if present. Otherwise it is an RFU, however, it is highly
continuously flows through while ADV# is low.
or the first active CLK edge whichever occurs first. .
on the first rising clock edge after ADV# assertion or on the rising edge of ADV# whichever
edge occurs first. In asynchronous read and asynchronous write modes, ADV# can be used to
latch the address, but can be held low for the entire operation as well.
unused flash chip enable should be treated as RFU.
recommended to always common F1-OE# and F2-OE# on the PCB.
During AD-Mux I/O operation, W18 A[MAX:16] can be treated as a NC pins, but C
exist on the pins.
During AD-Mux I/O operation, ADV# must remain deasserted during the data phase.
Signal Descriptions
128-Mbit W18 Family with Synchronous PSRAM
Order Number: 311760-10
L
November 2007
will
Note
s
1
1