AT52BC6402AT-70CU Atmel, AT52BC6402AT-70CU Datasheet
AT52BC6402AT-70CU
Specifications of AT52BC6402AT-70CU
Related parts for AT52BC6402AT-70CU
AT52BC6402AT-70CU Summary of contents
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... The AT52BC6402A(T) consists of a 64-Mbit Flash stacked with a 16-Mbit PSRAM in a single CBGA package. Stack Module Memory Contents Device Memory Combination AT52BC6402A(T) 64M Flash + 16M PSRAM Flash/PSRAM Read Access Asynchronous, Page Mode 64-Mbit Flash, 16-Mbit PSRAM (x16 I/O) AT52BC6402A AT52BC6402AT Preliminary Rev. 3441B–STKD–11/04 1 ...
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CBGA 66C4 – Top View Pin Configurations AT52BC6402A( A20 A11 A15 B A16 A8 A10 C WE A21 D PSGND RESET E WP VPP A19 PSOE G A18 ...
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Flash Description Device Operation 3441B–STKD–11/04 The 64-Mbit Flash memory is divided into multiple sectors and planes for erase opera- tions. The devices can be read or reprogrammed off a single 2.7V power supply, making them ideally suited for in-system ...
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AT52BC6402A(T) 4 ERASE: Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical “1”. The entire memory can be erased by using the Chip Erase command or individual planes or ...
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Table 1. Hardlock and Softlock Protection Configurations in Conjunction with WP Hard- Soft lock lock ...
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AT52BC6402A(T) 6 SECTOR PROTECTION DETECTION: A software method is available to determine if the sector protection Softlock or Hardlock features are enabled. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) ...
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Examining the toggle bit may begin at any time during a pro- gram cycle. Please see Table 3 on page 11 for more details. The toggle bit status bit should be used in ...
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AT52BC6402A(T) 8 128-BIT PROTECTION REGISTER: The 64-Mbit device contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and ...
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Figure 2. Data Polling Algorithm (Configuration Register = 00) START Read I/O7 - I/O0 Addr = VA YES I/O7 = Data I/O3, I/ YES Read I/O7 - I/O0 Addr = VA I/O7 = Data? NO Program/Erase ...
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Figure 4. Toggle Bit Algorithm (Configuration Register = 00) START Read I/O7 - I/O0 Read I/O7 - I/O0 NO Toggle Bit = Toggle? YES NO I/O3, I/ YES Read I/O7 - I/O0 Twice Toggle Bit = NO Toggle? ...
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Table 3. Status Bit Table I/O7 Configuration Register: 00/01 00/01 00/01 Read Address Plane A Plane B Plane C In While Programming I/O7/0 DATA DATA in Plane A Programming DATA I/O7/0 DATA in Plane B Programming DATA DATA I/O7/0 in ...
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Command Definition (Hex) Bus Command Sequence Cycles Addr Read 1 Addr Chip Erase 6 555 Plane Erase 6 555 Sector Erase 6 555 Word Program 4 555 (8) Dual-Word Program 5 555 Enter Single-pulse Program 6 555 Mode Single-pulse Word ...
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Absolute Maximum Ratings* Temperature under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages Except V PP (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V V Input Voltage PP with Respect to Ground ...
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Memory Organization – 64-Mbit Bottom Boot Size Plane Sector (Words) A SA0 4K A SA1 4K A SA2 4K A SA3 4K A SA4 4K A SA5 4K A SA6 4K A SA7 4K A SA8 32K A SA9 32K ...
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Memory Organization – 64-Mbit Bottom Boot (Continued) Size Plane Sector (Words) C SA90 32K C SA91 32K C SA92 32K C SA93 32K C SA94 32K C SA95 32K C SA96 32K C SA97 32K C SA98 32K C SA99 ...
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Memory Organization – 64-Mbit Top Boot Size Plane Sector (Words) D SA0 32K D SA1 32K D SA2 32K D SA3 32K D SA4 32K D SA5 32K D SA6 32K D SA7 32K D SA8 32K D SA9 32K ...
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Memory Organization – 64-Mbit Top Boot (Continued) Size Plane Sector (Words) B SA90 32K B SA91 32K B SA92 32K B SA93 32K B SA94 32K B SA95 32K A SA96 32K A SA97 32K A SA98 32K A SA99 ...
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DC and AC Operating Range Operating Temperature (Case) V Power Supply CC Operating Modes Mode CE OE Read V IL Burst Read V IL (3) Program/Erase V IL Standby/Program Inhibit Program Inhibit X X Output Disable X ...
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DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CMOS SB1 CC ( Active Current Read While Erase Current CCRE Read While ...
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AC Asynchronous Read Timing Characteristics Symbol Parameter t Access, Address to Data Valid ACC t Access Data Valid Data Valid OE t CE, OE High to Data Float DF t RESET to Output Delay ...
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AC Word Load Characteristics Symbol Parameter t Address Setup Time to WE and CE Low AS t Address Hold Time AH t Data Setup Time DS t Data Hold Time Low Pulse Width WP t ...
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Program Cycle Characteristics Symbol Parameter t Word Programming Time ( Word Programming Time (V BPVPP t Sector Erase Cycle Time (4K word sectors) SEC1 t Sector Erase Cycle Time (32K word sectors) SEC2 t Erase Suspend Time ES ...
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Data Polling Characteristics Symbol Parameter t Data Hold Time Hold Time OEH Output Delay OE t Write Recovery Time WR Notes: 1. These parameters are characterized and not 100% tested. 2. See t spec ...
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Table 4. Common Flash Interface Definition for 64-Mbit Device Address 64-Mbit Device 10h 0051h 11h 0052h 12h 0059h 13h 0002h 14h 0000h 15h 0041h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1Ah 0000h 1Bh 0027h 1Ch 0031h 1Dh 00B5h ...
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Table 4. Common Flash Interface Definition for 64-Mbit Device (Continued) Address 64-Mbit Device 41h 0050h 42h 0052h 43h 0049h 44h 0031h 45h 0030h 46h 008Fh 47h 0000h Top Boot or 0001h Bottom Boot 48h 0000h 49h 0000h 4Ah 0080h 4Bh ...
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PSRAM Description Features Block Diagram AT52BC6402A(T) 26 The device is a 16-Mbit 1T/1C PSRAM featured by high-speed operation and super low power consumption. The 16-Mbit device adopts one transistor memory cell and is orga- nized as 1,048,576 words by ...
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Absolute Maximum Ratings Symbol Parameter Input/Output Voltage IN OUT V Power Supply CC T Ambient Temperature A T Storage Temperature STG P Power Dissipation D T Ball Soldering Temperature and Time SOLDER Note: 1. Stresses greater than ...
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DC Electrical Characteristics V = 2.7V - 3.1V -30°C to 85°C ( Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Operating Power Supply Current CC I Average Operating Current CC1 I ...
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AC Characteristics V = 2.7V ~ 3.1V -30°C to 85°C (I), Unless Otherwise Specified Symbol Parameter Read Cycle 1 t Read Cycle Time Address Access Time Chip Select Access ...
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AC Test Loads Power-up Sequence Deep Power-down Entry Sequence Deep Power-down Exit Sequence State Diagram AT52BC6402A( OUT Ohm 0 Note: Including jig and scope capacitance. 1. Supply power. 2. Maintain stable power for longer than ...
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Timing Diagrams Power-up Sequence Timing V CC CS2 CS1 Note: Power-up time is defined when CS2 is kept high before V low level to high level, after V Deep Power-down Entry/Exit Sequence Timing Suspend 1 µs CS2 CS1 Note: When ...
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Read Cycle 1 ADDRESS CS1 CS2 V IH UB, LB PSOE HIGH-Z DATA OUT (1),(2),(4) Read Cycle 2, CS2 = V IH ADDRESS DATA OUT PREVIOUS DATA (1),(2),(4) Read Cycle 3, CS2 = V IH CS1 HIGH-Z DATA OUT ...
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Write Cycle 1 (PSWE Controlled) ADDRESS CS1 CS2 V IH UB,LB PSWE HIGH-Z DATA IN DATA OUT Write Cycle 2 (CS1 Controlled) ADDRESS CS1 CS2 V IH UB, LB PSWE HIGH-Z DATA IN HIGH-Z DATA OUT Notes write ...
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Write Cycle 3 (LB, UB Controlled) ADDRESS CS1 CS2 V IH UB, LB PSWE HIGH-Z DATA IN Notes: 1. The t is specified from the time satisfied both Although UB and LB are high state, it’s illegal ...
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Avoid Timing Abnormal Timing CS1 PSWE ADDRESS Avoidable Timing (1) CS1 PSWE ADDRESS Avoidable Timing (2) CS1 PSWE ADDRESS 3441B–STKD–11/04 The 16-Mbit PSRAM has a timing which is not supported at read operation. If your sys- tem has multiple invalid ...
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... Ordering Information t ACC (ns) Ordering Code AT52BC6402A-70CI 70 AT52BC6402AT-70CI AT52BC6402A-85CI 85 AT52BC6402AT-85CI 66C6 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA) AT52BC6402A(T) 36 Flash Boot Block PSRAM Bottom Top Bottom Top Package Type Package Operation Range Industrial 66C6 (-40° to 85°C) Industrial 66C6 (-40° to 85°C) ...
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Packaging Information 66C6 – CBGA Marked A1 Identifier E 1.10 REF Bottom View 2325 Orchard Parkway San Jose, CA 95131 R 3441B–STKD–11/04 D Top View D1 ...
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