LRS13012 Sharp Electronics, LRS13012 Datasheet
LRS13012
Manufacturer Part Number
LRS13012
Description
Manufacturer
Sharp Electronics
Datasheet
1.LRS13012.pdf
(1 pages)
Specifications of LRS13012
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Supplier Unconfirmed
P
LRS13012
Stacked Chip
FEATURES
• 4M Flash and 1M SRAM
• Flash memory access time 150 ns MAX.
• SRAM access time 70 ns MAX.
• Operating current
• Standby current
• Power supply 2.7 V to 3.6 V. (Block erase, byte write and lock-bit
• SRAM data retention current 1 µA MAX.
• Operating temperature -40°C to +85°C
• Fully static operation
• Three-state output
• Not designed or rated as radiation hardened
• 40-pin TSOP (TSOP40-P-0813) plastic package
• Flash Memory has P-type bulk silicon, and SRAM has N-type
DESCRIPTION
524,288 × 8 bit flash memory and 131,072 × 8 bit static RAM
in one package. It is fabricated using silicon-gate CMOS
process technology.
The information for this document is from Specification No. EL103011, issued on March 3, 1998.
Copyright ©1998, Sharp Electronics Corp. All rights reserved. All tradenames are the registered property of their respective owners. Specifications are subject to change without notice.
The LRS13012 is a combination memory organization as
RODUCT
– Flash memory read 12 mA MAX. (t
– Flash byte write 40 mA MAX.
– Flash block erase 37 mA MAX.
– SRAM operating 25 mA MAX. (t
– Flash memory 20 µA MAX.
– SRAM 30 µA MAX. (S- CE V
– Total standby current is the summation of flash memory’s
configuration operations with V
(V
bulk silicon
CCDR
(F- CE V
0.3 µA TYP. (T
standby current and SRAM’s standby current
= 3 V, T
CC
I
A
NFORMATION
– 0.2 V, RP 0.2 V)
, = 25°C)
A
= 25°C, V
CC
CC
cc
= 3 V, S- CE V
– 0.2 V)
CYCLE
3.0 V are not supported)
CYCLE
= 200 ns)
= 200 ns)
CC
– 0.2 V)
®
40-PIN TSOP PINOUT
PIN DESCRIPTION
40-PIN TSOP
F-A
I/O
APPLICATIONS:
A
17
Cellular Phone
RY/ BY
0
S-V
F-V
F-V
F-V
S-V
F-V
F- WE
S- WE
0
S-WE
F- CE
S- CE
F- OE
S- OE
GND
F-A
F-A
PIN
F-CE
Set Top Box
to A
RP
to F-A
to I/O
A
A
A
A
A
A
RP
CC
PP
CC
A
CC
CC
A
A
A
A
A
PP
18
17
15
14
13
12
10
Pager
11
9
8
7
6
5
4
PDA
16
18
7
11
12
13
14
1
3
4
6
8
10
15
16
17
18
19
20
2
5
7
9
Common Address Input Pins
Address Input Pins for Flash Memory
Chip Enable Input Pin for Flash Memory
Chip Enable Input Pin for SRAM
Write Enable Input Pin for Flash Memory
Write Enable Input Pin for SRAM
Output Enable Input Pin for Flash Memory
Output Enable Input Pin for SRAM
Common Data Input/Output Pins
Reset/Deep Power Down Input Pin for Flash Memory
Ready/Busy Output Pin for Flash Memory
Power Supply Pin for Flash Memory
Power Supply for Flash Memory Write/Erase
Power Supply Pin for SRAM
Common GND
DESCRIPTION
Integrated Circuits
40
39
38
37
36
35
34
33
32
30
29
28
27
26
25
24
23
22
31
21
F-WE
F-OE
RY/BY
A
A
I/O
I/O
I/O
F-V
GND
I/O
I/O
I/O
I/O
I/O
A
A
S-CE
A
S-OE
16
2
3
1
0
7
6
5
4
3
2
1
0
TOP VIEW
CC
LRS1301-1
Group
SMT98021
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