RD38F1020C0ZBL0S B48 Intel, RD38F1020C0ZBL0S B48 Datasheet - Page 9

• Manufacturer Part Number: RD38F1020C0ZBL0S B48
• Manufacturer: Intel

Specifications of RD38F1020C0ZBL0S B48

• Operating Supply Voltage (max): 3.3V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

1.4
Table 2.
Datasheet
A[20:0]
DQ[15:0]
F-CE#
S-CS
S-CS
F-OE#
S-OE#
F-WE#
S-WE#
S-UB#
S-LB#
Symbol
1
2
#
OUTPUT
INPUT /
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Signal Definitions
Table 2
Intel
Type
C3 SCSP Flash Memory
®
Intel
Advanced+ Boot Block SCSP Ball Descriptions (Sheet 1 of 2)
defines the signals shown in
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or
erase cycle.
DATA INPUTS/OUTPUTS:
The data balls float to tristate when the chip is deselected or the outputs are disabled.
FLASH CHIP ENABLE: Activates the flash internal control logic, input buffers, decoders, and
sense amplifiers.
SRAM CHIP SELECT1: Activates the SRAM internal control logic, input buffers, decoders, and
sense amplifiers.
SRAM CHIP SELECT2: Activates the SRAM internal control logic, input buffers, decoders, and
sense amplifiers.
FLASH OUTPUT ENABLE: Enables flash memory outputs through the data buffers during a read
operation. F-OE# is active low.
SRAM OUTPUT ENABLE: Enables SRAM outputs through the data buffers during a read
operation. S-OE# is active low.
FLASH WRITE ENABLE: Controls writes to the flash memory command register and memory
array. F-WE# is active low. Addresses and data are latched on the rising edge of the second
F-WE# pulse.
SRAM WRITE ENABLE: Controls writes to the SRAM memory array. S-WE# is active low.
SRAM UPPER BYTE ENABLE: Enables the upper byte for SRAM (DQ
S-UB# is active low.
SRAM LOWER BYTE ENABLE: Enables the lower byte for SRAM (DQ
S-LB# is active low.
®
• 2-Mbit : A[16:0]
• 4-Mbit : A[18:0]
• 16-Mbit : A[19:0]
• 32-Mbit A[20:0]
• Inputs array data for SRAM write operations and on the second F-CE# and F-WE# cycle
• Inputs commands to the flash memory Command User Interface when F-CE# and F-WE# are
• Data is internally latched.
• Outputs array, configuration, and status register data.
• F-CE# is active low.
• F-CE# high deselects the flash memory device and reduces power consumption to standby
• S-CS1# is active low.
• S-CS1# high deselects the SRAM memory device and reduces power consumption to standby
• S-CS2 is active high.
• S-CS2 low deselects the SRAM memory device and reduces power consumption to standby
Advanced+ Boot Block Flash Memory (C3) SCSP Family
during a flash program command.
asserted.
levels.
levels.
levels.
Order Number: 252636, Revision: 004
Figure 1 “66-Ball SCSP Package Ballout” on page
Name and Function
8
0
–DQ
–DQ
15
7
).
).
26 Aug 2005
8.
9