LTC4251-1CS6#PBF Linear Technology, LTC4251-1CS6#PBF Datasheet - Page 12

• Manufacturer Part Number: LTC4251-1CS6#PBF
• Manufacturer: Linear Technology

Specifications of LTC4251-1CS6#PBF

• Family Name: LTC4251-1
• Package Type: TSOT-23
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Height (mm): 0.9mm
• Product Length (mm): 2.9mm
• Mounting: Surface Mount
• Pin Count: 6
• Lead Free Status / RoHS Status: Compliant

LTC4251/LTC4251-1/
LTC4251-2
APPLICATIO S I FOR ATIO
GATE
GATE is pulled low to V
conditions: in UVLO, during the initial timing cycle, in an
overvoltage condition, or when the LTC4251/LTC4251-1/
LTC4251-2 are latched off after a short-circuit. When
GATE turns on, a 58µA current source charges the MOSFET
gate and any associated external capacitance. V
gate drive to no more than 14.5V.
Gate-drain capacitance (C
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at V
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating C
capacitor C
for the analog current limit loop.
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier, and
the fast current limit (FCL) comparator. Each of these three
measures the potential of SENSE relative to V
exceeds 50mV, the CB comparator activates the 230µA
TIMER pull-up. At 100mV, the ACL amplifier servos the
MOSFET current, and at 200mV the FCL comparator
abruptly pulls GATE low in an attempt to bring the MOSFET
current under control. If any of these conditions persists
long enough for TIMER to charge C
tion (2)), the LTC4251/LTC4251-1/LTC4251-2 latch off
and pull GATE low.
12
Figure 3. Circuit Breaker Response Time
C
is adequate. C
0.01
0.1
10
1
0
GD
U
20
. Instead, a smaller value (≥10nF)
FAULT DUTY CYCLE, D (%)
C
T
(µF)
t
EE
U
GD
C
40
=
(235.8 • D) – 5.8
also provides compensation
under any of the following
) feed through at the first
60
4
W
T
80
to 4V (see Equa-
425112 F03
100
EE
U
. If SENSE
IN
limits
IN
,
If the SENSE pin encounters a voltage greater than 100mV,
the ACL amplifier will servo GATE downwards in an
attempt to control the MOSFET current. Since GATE over-
drives the MOSFET in normal operation, the ACL amplifier
needs time to discharge GATE to the threshold of the
MOSFET. For a mild overload, the ACL amplifier can
control the MOSFET current, but in the event of a severe
overload the current may overshoot. At SENSE = 200mV,
the FCL comparator takes over, quickly discharging the
GATE pin to near V
ACL amplifier takes over. All the while TIMER is running.
The effect of FCL is to add a nonlinear response to the
control loop in favor of reducing MOSFET current.
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop, and GATE under-
shoots. A zero in the loop (resistor R
gate capacitor) helps the ACL amplifier recover.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load-side low impedance
short is shown in Figure 4. Initially, the current overshoots
the analog current limit level of V
as the GATE pin works to bring V
The overshoot glitches the backplane in the negative
direction, and when the current is reduced to 100mV/R
the backplane responds by glitching in the positive
direction.
TIMER commences charging C
current limit loop maintains the fault current at 100mV/R
which in this case is 5A (Trace 2). Note that the backplane
voltage (Trace 1) sags under load. When C
GATE turns off, the load current drops to zero and the
backplane rings up to over 100V. The positive peak is
usually limited by avalanche breakdown in the MOSFET,
and can be further limited by adding a zener diode across
the input from – 48V to – 48RTN, such as Diodes Inc.
SMAT70A.
A low-impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 4, Trace 1, can
rob charge from output capacitors on adjacent cards. When
the faulty card shuts down, current flows in to refresh the
EE
potential. FCL then releases, and the
T
GS
(Trace 4) while the analog
SENSE
under control (Trace 3).
C
= 100mV (Trace 2)
in series with the
T
reaches 4V,
425112fa
S
S
,