AD1893JNZ Analog Devices Inc, AD1893JNZ Datasheet - Page 5

• Manufacturer Part Number: AD1893JNZ
• Manufacturer: Analog Devices Inc

Specifications of AD1893JNZ

• Lead Free Status / RoHS Status: Compliant

REV. A
AD1893 PIN LIST
Serial Input Interface
Pin Name DIP
DATA_I
BCLK_I
WCLK_I
LR_I
Serial Output Interface
Pin Name DIP
DATA_O
BCLK_O
WCLK_O
LR_O
Input Control Signals
Pin Name DIP
BKPOL_I
MODE0_I 11
MODE1_I 12
BKPOL_I
MODE0_I
MODE1_I
XTAL_O
WCLK_I
DATA_I
BCLK_I
XTAL_I
RESET
LR_I
GND
GND
V
NC
DD
10
11
12
13
14
1
2
3
4
5
6
7
8
9
3
4
5
6
23
26
25
24
10
NC = NO CONNECT
LQFP I/O
43
2
3
4
LQFP I/O
30
35
32
31
LQFP I/O Description
9
10
13
FIFO
SERIAL IN
TRACKING
CLOCK
MULT
I
I
I
I
O
I
I
I
I
I
I
DIP
ACCUM
SERIAL OUT
COEF ROM
Description
Serial input, MSB first, containing two channels of 4 to 16 bits of twos-complement data per
channel.
Bit clock input for input data. Need not run continuously; may be gated or used in a burst fashion.
Word clock input for input data. This input is rising edge sensitive. (Not required in LR input
data clock triggered modes.)
Left/right clock input for input data. Must run continuously.
Description
Serial output, MSB first, containing two channels of 4- to 24-bits of twos-complement data per
channel.
Bit clock input for output data. Need not run continuously; may be gated or used in a burst
fashion.
Word clock input for output data. This input is rising edge sensitive. (Not required in LR output
data clock triggered modes.)
Left/right clock input for output data. Must run continuously.
Bit clock polarity. LO: Normal mode. Input data is sampled on rising edges of BCLK_I. HI:
Inverted mode. Input data is sampled on falling edges of BCLK_I.
Serial mode zero control for input port.
Serial mode one control for input port.
MODE0_I MODE1_I
0
0
1
1
AD1893
0
1
0
1
28
27
26
25
24
18
23
22
21
20
19
17
16
15
PIN CONFIGURATIONS
SETSLW
PWRDWN
BCLK_O
WCLK_O
LR_O
DATA_O
V
GND
NC
BKPOL_O
MODE0_O
MODE1_O
MUTE_O
MUTE_I
DD
Left-justified, no MSB delay, LR_I clock triggered.
Left-justified, MSB delay, LR_I clock triggered.
Right-justified, MSB delayed 16 bit clock periods from LR_I transition.
WCLK_I triggered, no MSB delay.
–5–
NC = NO CONNECT
BKPOL_I
MODE0_I
WCLK_I
BCLK_I
LR_I
GND
V
NC
NC
NC
NC
DD
10
11
1
3
4
7
2
5
6
8
9
44
12 13
43
42
14
SERIAL IN
FIFO
15 16 17
41
40
AD1893
TRACKING
LQFP
ACCUM
CLOCK
MULT
39 38
18
COEF ROM
SERIAL OUT
37
19
36 35 34
20
21 22
AD1893
33
32
31
30
29
28
27
26
25
24
23
NC
WCLK_O
LR_O
DATA_O
NC
V
GND
NC
BKPOL_O
MODE0_O
NC
DD