HSP50214BVI Intersil, HSP50214BVI Datasheet - Page 53
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HSP50214BVI
Manufacturer Part Number
HSP50214BVI
Description
Manufacturer
Intersil
Datasheet
1.HSP50214BVI.pdf
(62 pages)
Specifications of HSP50214BVI
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HSP50214BVIZ
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
HSP50214BVIZ
Manufacturer:
INTERSIL
Quantity:
20 000
POSITION
POSITION
17-15
14-12
31-26
23-22
21-20
16-14
13-12
11-9
BIT
BIT
8-6
5-3
2-0
25
24
19
18
17
CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION
Link Following Q Data The serial data word, or link, following the Q data word is selected using Table 12
Link Following
Magnitude Data
Link Following Phase
Data
Link Following
Frequency Data
Link Following AGC
Level Data
Link Following Timing
Error Data
Reserved
Data Source for Least
Significant Bytes of
AOUT and BOUT
Buffered Output Mode
Interface
AOUT Direct Parallel
Output Mode Data
Source
BOUT Direct Parallel
Output Mode Data
Source
Serial Output Sync
Polarity
Serial Output Clock
Polarity
Serial Output Sync
Position
Serial Out Clock
Divider
I Data Serial Output
Tag Bit
CONTROL WORD 19: SERIAL OUTPUT ORDER (SYNCHRONIZED TO PROCCLK) (Continued)
FUNCTION
FUNCTION
53
(see Output Section).
The serial data word, or link, following the MAG data word is selected using Table 12
(see Output Section).
The serial data word, or link, following the PHAS data word is selected using Table 12
(see Output Section).
The serial data word, or link, following the FREQ data word is selected using Table 12
(see Output Section).
The serial data word, or link, following the AGC data word is selected using Table 12
(see Output Section).
The serial data word, or link, following the TIMER data word is selected using Table 12
(see Output Section).
Reserved.
Output LSBytes, bits (7:0), of AOUT and BOUT can provide:
0- Buffer RAM Mode Output or,
1- Parallel Direct Mode Output.
Buffered Mode Output interfaces to either:
0- 8-bit μP (address = μP ASEL(5:#); CLK = μP RAM read).
1- 16-bit μP (address = SEL(2:0); CLK = OEBL).
The data word sent by the Direct Parallel Output Mode to AOUT is:
00- I Data. (2’s complement)
01- Magnitude. (O; unsigned binary)
1X- Frequency. (2’s complement)
The data word sent by the Direct Parallel Output Mode to BOUT is:
00- Q Data (2’s complement).
01- Phase (2’s complement).
1X- Magnitude (O; unsigned binary).
0- Normal Sync Mode (active high).
1- Sync Inverted (active low).
0- Output Clock Inverted rising edge aligns with data transitions.
1- Output Clock Normal falling edge aligns with data transitions.
0- Sync is asserted one bit time after the last bit of the serial word (Late Mode).
1- Sync is asserted one bit time prior to the first bit of the serial word (Early Mode).
000- Serial Output at PROCCLK/16.
001- Serial Output at PROCCLK/8.
010- Serial Output at PROCCLK/4.
011- Serial Output at PROCCLK/2.
1XX- Serial Output at PROCCLK rate.
00- No Tag Bit. LSB of word is passed.
01- 0 Tag Bit. LSB of word is set to zero.
1X- 1 Tag Bit. LSB of word is set to one.
(SYNCHRONIZED WITH PROCCLK)
0
HSP50214B
1
DESCRIPTION
DESCRIPTION
May 1, 2007
FN4450.4