ADE7756ANZ Analog Devices Inc, ADE7756ANZ Datasheet - Page 30

• Manufacturer Part Number: ADE7756ANZ
• Manufacturer: Analog Devices Inc

Specifications of ADE7756ANZ

• Lead Free Status / RoHS Status: Compliant

ADE7756
Mode Register (06H)
The ADE7756 functionality is configured by writing to the MODE register. Table VI summarizes the functionality of each bit in the
MODE register.
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
12, 11
14, 13
15
(TEST MODE SELECTION SHOULD BE SET TO 0)
(WAVE FORM SELECTION FOR SAMPLE MODE)
(SHORT THE ANALOG INPUTS ON CHANNEL 2)
(SHORT THE ANALOG INPUTS ON CHANNEL 1)
(WAVE FORM SAMPLES OUTPUT DATA RATE)
Bit
Mnemonic
DISHPF
DISLPF2
DISCF
DISSAG
ASUSPEND
TEMPSEL
SWRST
CMODE
DISCH1
DISCH2
SWAP
DTRT1, 0
WAVSEL1, 0
TEST1
(SWAP CH1 AND CH2 ADCs)
00 = 27.9kSPS (CLKIN/128)
01 = 14.4kSPS (CLKIN/256)
11 = 3.6kSPS (CLKIN/1024)
10 = 7.2kSPS (CLKIN/512)
01 = RESERVED
00 = LPF2
WAVSEL
10 = CH1
11 = CH2
DISCH2
DISCH1
TEST 1
SWAP
DTRT
The HFP (High-Pass Filter) in Channel 1 is disabled when this bit is set.
The LPF (Low-Pass Filter) after the multiplier (LPF2) is disabled when this bit is set.
The frequency output CF is disabled when this bit is set.
The line voltage Sag detection is disabled when this bit is set.
By setting this bit to Logic 1, both ADE7756’s A/D converters can be turned off. In normal
The temperature conversion starts when this bit is set to one. This bit is automatically reset to
Software Chip Reset. A data transfer should not take place to the ADE7756 for at least 18 µs
Setting this bit to a Logic 1 places the chip in calibration mode.
ADC 1 (Channel 1) inputs are internally shorted together.
ADC 2 (Channel 2) inputs are internally shorted together.
By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the
Writing a Logic 1 to this bit position places the ADE7756 in test mode. This is intended for
Description
operation, this bit should be left at Logic 0. All digital functionality can be stopped by sus-
pending the clock signal at CLKIN pin.
zero when the temperature conversion is finished.
after a software reset.
analog inputs V1P and V1N are connected to ADC 2.
These bits are used to select the Waveform Register update rate.
DTRT 1
0
0
1
1
These bits are used to select the source of the sampled data for the Waveform Register
WAVSEL1
0
0
1
1
factory testing only and should be left at zero.
15
0
14
0
13
0
REGISTER CONTENTS SHOW POWER-ON DEFAULTS
12
0
Table VI. Mode Register
DTRT0
0
1
0
1
WAVSEL0
0
1
0
1
11
0
10
0
MODE REGISTER
0
9
8
0
0
7
Update Rate
27.9 kSPS (CLKIN/128)
14 kSPS (CLKIN/256)
7 kSPS (CLKIN/512)
3.5 kSPS (CLKIN/1024)
Source
Active Power signal (output of LPF2)
RESERVED
Channel 1
Channel 2
6
0
5
0
4
0
3
1
2
1
1
0
0
0
ADDR: 06H
DISHPF
(DISABLE HPF IN CHANNEL 1)
DISLPF2
(DISABLE LPF2 AFTER MULTIPLIER)
DISCF
(DISABLE FREQUENCY OUTPUT CF)
DISSAG
(DISABLE SAG OUTPUT)
ASUSPEND
(SUSPEND CH1 AND CH2 ADCs)
TEMPSEL
(START TEMPERATURE SENSING)
SWRST
(SOFTWARE CHIP RESET)
CMODE
(CALIBRATION MODE)