LTC1753CSW#TRM Linear Technology, LTC1753CSW#TRM Datasheet - Page 19

• Manufacturer Part Number: LTC1753CSW#TRM
• Manufacturer: Linear Technology

Specifications of LTC1753CSW#TRM

• Lead Free Status / RoHS Status: Not Compliant

APPLICATIO S I FOR ATIO
possible. It should also be located as close as possible
above (or below) the power ground plane. Some of the
phase shift problem can be solved by taking the AC
feedback locally at the regulator output while still taking
the DC feedback at the point of load. This permits accurate
DC regulation while still maintaining reasonable phase
margin. This is done by connecting the top of phase lead
capacitor, C2, locally at the regulator output while con-
necting the SENSE pin to the load. The corner frequency
1/(2 • R2 • C2) must be significantly less than the
resonant frequency of the parasitic inductance and the
output capacitance 1/(2 • L
layouts may require R
crease the slew rate of the feedforward path. In general, an
empirical approach to compensating this type of loop will
be best since it will be very difficult to estimate the parasitic
inductance of the power path analytically. It should be
noted that if the circuit can have a wide range of output
capacitance, this can be dangerous technique to employ
since the double-pole frequency will move as the load
capacitance changes. Be sure to verify stability with all
possible combinations of output capacitance.
Figure 8. Feedback Connections for Remote Sense Applications
R
C
C
C
COMP
Q1
Q2
10
C1
L
O
LTC1753
+
U
ERR
C
OUT
C2
+
–
, a small series resistor, to de-
U
DAC
DIST
1 F
• C
6
W
R2
R1
SENSE
LOAD
L
DIST
1753 F08
1 F
V
11
). Certain board
FB
R
+
U
C2
C2
C
LOAD
LOAD
VID0 to VID4, PWRGD and FAULT
The digital inputs (VID0 to VID4) program the internal DAC
which in turn controls the output voltage. These digital
input controls are intended to be static and are not
designed for high speed switching. Forcing V
from a high to a low voltage by changing the VID
quickly can cause FAULT to trip.
Figure 9 shows the relationship between the V
PWRGD and FAULT. To prevent PWRGD from interrupting
the CPU unnecessarily, the LTC1753 has a built-in t
delay to prevent noise at the SENSE pin from toggling
PWRGD. The internal time delay is designed to take about
500 s for PWRGD to go low and 1ms for it to recover.
Once PWRGD goes low, the internal circuitry watches for
the output voltage to exceed 113% of the rated voltage. If
this happens, FAULT will be triggered. Once FAULT is
triggered, G1 and G2 will be forced low immediately and
the LTC1753 will remain in this state until V
supply is recycled or OUTEN is toggled.
RATED V
PWRGD
FAULT
– 3%
13%
OUT
3%
t
PWRBAD
Figure 9. PWRGD and FAULT
V
OUT
t
PWRGD
t
FAULT
LTC1753
OUT
OUT
CC
1753 F09
voltage,
PWRBAD
19
to step
power
n
pins
1753fa