XC6VSX475T-1FFG1759C Xilinx Inc, XC6VSX475T-1FFG1759C Datasheet - Page 9
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XC6VSX475T-1FFG1759C
Manufacturer Part Number
XC6VSX475T-1FFG1759C
Description
XC6VSX475T-1FFG1759C
Manufacturer
Xilinx Inc
Series
Virtex™ 6 SXTr
Datasheet
1.XC6VHX250T-1FFG1154C.pdf
(11 pages)
Specifications of XC6VSX475T-1FFG1759C
Number Of Logic Elements/cells
476160
Number Of Labs/clbs
37200
Total Ram Bits
39223296
Number Of I /o
840
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1759-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6VSX475T-1FFG1759C
Manufacturer:
XILINX
Quantity:
210
Company:
Part Number:
XC6VSX475T-1FFG1759C
Manufacturer:
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Quantity:
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Company:
Part Number:
XC6VSX475T-1FFG1759C
Manufacturer:
Xilinx Inc
Quantity:
10 000
This block is highly configurable to system design requirements and can operate 1, 2, 4, or 8 lanes at the 2.5 Gb/s data rate
and the 5.0 Gb/s data rate. For high-performance applications, advanced buffering techniques of the block offer a flexible
maximum payload size of up to 1024 bytes. The integrated block interfaces to the GTX transceivers for serial connectivity,
and to block RAMs for data buffering. Combined, these elements implement the Physical Layer, Data Link Layer, and
Transaction Layer of the PCI Express protocol.
Xilinx provides a light-weight, configurable, easy-to-use LogiCORE™ wrapper that ties the various building blocks (the
integrated block for PCI Express, the GTX transceivers, block RAM, and clocking resources) into an Endpoint or Root Port
solution. The system designer has control over many configurable parameters: lane width, maximum payload size, FPGA
logic interface speeds, reference clock frequency, and base address register decoding and filtering.
More information and documentation on solutions for PCI Express designs can be found at:
10/100/1000 Mb/s Ethernet Controller (2500 Mb/s Supported)
An integrated Tri-mode Ethernet MAC (TEMAC) block is easily connected to the FPGA logic, the GTX transceivers, and the
SelectIO resources. This TEMAC block saves logic resources and design effort. All of the Virtex-6 devices (except the
XC6VLX760) have four TEMAC blocks, implementing the link layer of the OSI protocol stack. The CORE Generator™
software GUI helps to configure flexible interfaces to GTX transceiver or SelectIO technology, to the FPGA logic, and to a
microprocessor (when required). The TEMAC is designed to the IEEE Std 802.3-2005 specification. 2500 Mb/s support is
also available.
Virtex-6 FPGA Ordering Information
The Virtex-6 FPGA ordering information shown in
X-Ref Target - Figure 1
DS150 (v2.2) January 28, 2010
Advance Product Specification
http://www.xilinx.com/technology/protocols/pciexpress.htm
(-1, -L1
Note:
1) -L1 is the ordering code for the lower power version.
2) -3 speed grades are not available in all devices
Example: XC6VLX240T-1FFG1156C
-L1 is not available in the Virtex-6 HXT devices. See
the Virtex-6 FPGA data sheet for more information.
Speed Grade
Device Type
(1)
, -2, -3
(2)
)
Figure 1: Virtex-6 FPGA Ordering Information
Figure 1
www.xilinx.com
applies to all packages including Pb-Free.
Number of Pins
Pb-Free
Package Type
Temperature Range:
C = Commercial (T
I = Industrial (T
J
= –40°C to +100°C)
J
= 0°C to +85°C)
Virtex-6 Family Overview
DS150_01_090209
9