XC2C128-7TQG144C Xilinx Inc, XC2C128-7TQG144C Datasheet - Page 8
![CPLD CoolRunner™-II Family 3K Gates 128 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 144-Pin TQFP EP](/photos/6/70/67094/144tqfp_sml.jpg)
XC2C128-7TQG144C
Manufacturer Part Number
XC2C128-7TQG144C
Description
CPLD CoolRunner™-II Family 3K Gates 128 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 144-Pin TQFP EP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Specifications of XC2C128-7TQG144C
Package
144TQFP EP
Family Name
CoolRunnerÂ-II
Device System Gates
3000
Number Of Macro Cells
128
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
100
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
152 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
0 to 70 °C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
3000
Number Of I /o
100
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Features
JTAG
Voltage
1.8V
Memory Type
CMOS
Case
TQFP144
Dc
04+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1397
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2C128-7TQG144C
Manufacturer:
XILINX
Quantity:
14
CoolRunner-II CPLD Family
nally generated DataGATE control logic can be assigned to
this I/O pin with the BUFG=DATA_GATE attribute.
Global Signals
Global signals, clocks (GCK), sets/resets (GSR), and output
enables (GTS), are designed to strongly resemble each
other. This approach enables design software to make the
best utilization of their capabilities. Each global capability is
supplemented by a corresponding product term version.
Figure 7
trees. The pin input is buffered, then drives multiple internal
global signal traces to deliver low skew and reduce loading
delays. GCK, GSR, and GTS can also be used as general
8
shows the common structure of the global signal
Figure 6: DataGATE Architecture (output drivers not shown)
Latch
Latch
To AIM
To AIM
MC16
MC16
MC1
MC2
MC1
MC2
PLA
PLA
DataGATE Assertion Rail
www.xilinx.com
AIM
purpose I/Os if they are not needed as global signals. The
DataGATE assertion rail is also a global signal.
Figure 7: Global Clocks (GCK), Sets/Resets (GSR), and
PLA
PLA
MC16
MC16
MC1
MC2
MC1
MC2
Output Enables (GTS)
To AIM
To AIM
To AIM
DS090 (v3.1) September 11, 2008
Latch
Latch
Latch
DS090_07_101001
Product Specification
DS090_06_111201
R