DS90C365AMT National Semiconductor, DS90C365AMT Datasheet
DS90C365AMT
Specifications of DS90C365AMT
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DS90C365AMT Summary of contents
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... Up to 223.125 Megabytes/sec bandwidth ■ 345 mV (typ) swing LVDS devices for low EMI ■ PLL requires no external components ■ Compliant to TIA/EIA-644 LVDS standard ■ Low profile 48-lead TSSOP package DS90C365A Order Number DS90C365AMT See NS Package Number MTD48 201005 August 6, 2008 20100539 www.national.com ...
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... Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 sec) Maximum Package Power Dissipation Capacity @ 25°C MTD48 (TSSOP) Package: DS90C365AMT Package Derating: DS90C365AMT 16 mW/°C above +25°C Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter LVCMOS/LVTTL DC SPECIFICATIONS V ...
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Symbol Parameter ICCTG Transmitter Supply Current 16 Grayscale ICCTZ Transmitter Supply Current Power Down Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the ...
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Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol LLHT LVDS Low-to-High Transition Time (Figure 4) LHLT LVDS High-to-Low Transition Time (Figure 4) TPPos0 Transmitter Output Pulse Position (Figure 12) (Note 5) TPPos1 Transmitter Output ...
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Symbol TCCD TxCLK IN to TxCLK OUT Delay. Measure from TxCLK IN edge to immediatley crossing poing of differential TxCLK OUT by following the postive TxCLK OUT. 50% duty cycle input clock is assumed. (Figure 7) Measure from TxCLK IN ...
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AC Timing Diagrams FIGURE 2. “16 Grayscale” Test Pattern - DS90C365A (Notes 8, 9, 10) Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O. Note 8: The 16 grayscale test ...
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FIGURE 3. DS90C365A (Transmitter) LVDS Output Load. 5pF is showed as board loading FIGURE 4. DS90C365A (Transmitter) LVDS Transition Times FIGURE 5. DS90C365A (Transmitter) Input Clock Transition Time FIGURE 6. DS90C365A (Transmitter) Setup/Hold and High/Low Times with R_FB pin = ...
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FIGURE 8. DS90C365A (Transmitter) Clock In to Clock Out Delay with R_FB pin = GND FIGURE 9. DS90C365A (Transmitter) Phase Lock Loop Set Time FIGURE 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90C365A www.national.com 20100535 20100514 ...
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FIGURE 11. Transmitter Power Down Delay FIGURE 12. Transmitter LVDS Output Pulse Position Measurement - DS90C365A 20100518 9 20100537 www.national.com ...
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DS90C365A MTD48 (TSSOP) Package Pin Descriptions — FPD Link Transmitter Pin Name I/O No. TxIN I 21 LVTTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3control lines—FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, ...
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... POWER SOURCES SEQUENCE In typical applications recommended to have V the V and PLL V CC separate de-coupling bypass capacitor groups. There is no requirement on which VCC entering the device first. DS90C365AMT 20100540 11 , LVDS CC from the same power source with three CC www.national.com ...
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Typical Application Truth Table www.national.com TABLE 1. Programmable Transmitter (DS90C365A) Pin Condition Strobe Status R_FB R_FB = V Rising edge strobe CC R_FB R_FB = GND or NC Falling edge strobe 12 20100503 ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Molded Thin Shrink Small Outline Package, JEDEC Dimensions in millimeters only Order Number DS90C365AMT NS Package Number MTD48 13 www.national.com ...
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