DS90CF388VJD National Semiconductor, DS90CF388VJD Datasheet - Page 21

• Manufacturer Part Number: DS90CF388VJD
• Description: IC,Serial-to-Parallel Converter,CMOS,TQFP,100PIN
• Manufacturer: National Semiconductor

Specifications of DS90CF388VJD

• Number Of Elements: 8
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 100mV
• Diff. Input Low Threshold Volt: -100mV
• Output Type: Flat Panel Display
• Differential Output Voltage: 450mV
• Operating Temp Range: -10C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Number Of Receivers: 8
• Number Of Drivers: 48
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Not Compliant

Applications Information
HOW TO CONFIGURE THE DS90C387 AND DS90CF388
FOR MOST COMMON APPLICATION
1. To configure for single input pixel-to-dual pixel output
application, the DS90C387 “DUAL” pin must be set to 1/2
Vcc=1.65V. This may be implemented using pull-up and
pull-down resistors of 10kΩ each as shown in Figure 16. A
capacitor between “DUAL” pin and ground will help to stabi-
lize the DC voltage level in a noisy environment. In this
configuration, the input signals (single pixel) are split into
odd and even pixel (dual pixels) starting with the odd (first)
pixel outputs A0-to-A3 the next even (second) pixel outputs
to A4-to-A7. The splitting of the data signal also starts with
DE (data enable) transitioning from logic low to high indicat-
ing active data. The "R_FDE" pin must be set high in this
case. This is supported in DC Balanced and non-DC Bal-
anced (BAL=low or high) data transmission. The number of
clock cycles during blanking must be an EVEN number. This
configuration will allow the user to interface to an LDI re-
ceiver (DS90CF388) or if in the non-DC Balanced mode
(BAL=low)
(DS90CF384A). The DC Balance feature is recommended
for monitor applications which require
length. Notebook applications should disable this feature to
reduce the current consumption of the chipset. Note that
only the DS90C387/DS90CF388 support the DC Balance
data transmission feature.
2. To configure for single pixel or dual pixel application using
the DS90C387/DS90CF388, the “DUAL” pin must be set to
Note 19: This is based on testing with standard shield twisted pair cable. The amount of pre-emphasis will vary depending on the type of cable, length and operating
frequency.
DC Balance
In the Balanced operating modes, in addition to pixel and
control information an additional bit is transmitted on every
LVDS data signal line during each cycle of active data as
shown inFigure 18 . This bit is the DC Balance bit (DCBAL).
The purpose of the DC Balance bit is to minimize the short-
and long-term DC bias on the signal lines. This is achieved
by selectively sending the pixel data either unmodified or
inverted.
then
two
FPD-Link
1MΩ or NC
Frequency
112MHz
112MHz
TABLE 5. PRE-EMPHASIS DC VOLTAGE LEVEL WITH (RPRE)
80MHz
80MHz
65MHz
56MHz
100Ω
50kΩ
Rpre
9kΩ
3kΩ
1kΩ
TABLE 6. PRE-EMPHASIS NEEDED PER CABLE LENGTH
’notebook’
>
2meters of cable
receivers
Resulting PRE Voltage
PRE Voltage
0.75V
1.0V
1.5V
2.0V
2.6V
1.0V
1.5V
1.0V
1.2V
1.5V
1.0V
Vcc
21
Vcc (dual) or Gnd (single). In dual mode, the transmitter-
DS90C387 has two LVDS clock outputs enabling an inter-
face to two FPD-Link ’notebook’ receivers (DS90CF384A or
DS90CF386). In single mode, outputs A4-to-A7 and CLK2
are disabled which reduces power dissipation. Both single
and dual mode also support the DC Balance data transmis-
sion feature, which should only be used for monitor applica-
tion.
The DS90CF388 is able to support single or dual pixel
interface up to 112MHz operating frequency. This receiver
may also be used to interface to a VGA controller with an
integrated LVDS transmitter without DC Balance data trans-
mission. In this case, the receivers “BAL” pin must be tied
low (DC Balance disabled).
NEW FEATURES DESCRIPTION
Pre-Emphasis
adds extra current during LVDS logic transition to reduce the
cable loading effects. Pre-emphasis strength is set via a DC
voltage level applied from min to max (0.75V to Vcc) at the
“PRE” pin. A higher input voltage on the ”PRE” pin increases
the magnitude of dynamic current during data transition. The
“PRE” pin requires one pull-up resistor (Rpre) to Vcc in order
to set the DC level. There is an internal resistor network,
which cause a voltage drop. Please refer to the tables below
to set the voltage level.
The value of the DC Balance bit is calculated from the
running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word shall
be calculated by subtracting the number of bits of value 0
from the number of bits value 1 in the current word. Initially,
the running word disparity may be any value between +7 and
−6. The running word disparity shall be calculated as a
continuous sum of all the modified data disparity values,
where the unmodified data disparity value is the calculated
data disparity minus 1 if the data is sent unmodified and 1
Typical cable length
100% pre-emphasis
50% pre-emphasis
Standard LVDS
10 meters
10 meters
2 meters
5 meters
2 meters
7 meters
Effects
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