5962-8754001CA Analog Devices Inc, 5962-8754001CA Datasheet

5962-8754001CA

Manufacturer Part Number

5962-8754001CA

Description

Manufacturer

Analog Devices Inc

Datasheet

1.5962-8754001CA.pdf (6 pages)

Specifications of 5962-8754001CA

Number Of Sample And Hold Elements

Power Supply Requirement

Dual

Single Supply Voltage (typ)

Not RequiredV

Single Supply Voltage (min)

Not RequiredV

Single Supply Voltage (max)

Not RequiredV

Mounting

Through Hole

Pin Count

Lead Free Status / RoHS Status

Not Compliant

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REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

PRODUCT DESCRIPTION

The AD585 is a complete monolithic sample-and-hold circuit

consisting of a high performance operational amplifier in series

with an ultralow leakage analog switch and a FET input inte-

grating amplifier. An internal holding capacitor and matched

applications resistors have been provided for high precision and

applications flexibility.

The performance of the AD585 makes it ideal for high speed

10- and 12-bit data acquisition systems, where fast acquisition

time, low sample-to-hold offset, and low droop are critical. The

AD585 can acquire a signal to 0.01% in 3 s maximum, and

then hold that signal with a maximum sample-to-hold offset of

3 mV and less than 1 mV/ms droop, using the on-chip hold

capacitor. If lower droop is required, it is possible to add a

larger external hold capacitor.

The high speed analog switch used in the AD585 exhibits

aperture jitter of 0.5 ns, enabling the device to sample full scale

(20 V peak-to-peak) signals at frequencies up to 78 kHz with

12-bit precision.

The AD585 can be used with any user-defined feedback net-

work to provide any desired gain in the sample mode. On-chip

precision thin-film resistors can be used to provide gains of +1,

–1, or +2. Output impedance in the hold mode is sufficiently

low to maintain an accurate output signal even when driving the

dynamic load presented by a successive-approximation A/D

converter. However, the output is protected against damage

from accidental short circuits.

The control signal for the HOLD command can be either active

high or active low. The differential HOLD signal is compatible

with all logic families, if a suitable reference level is provided. An

on-chip TTL reference level is provided for TTL compatibility.

FEATURES

3.0 s Acquisition Time to

Low Droop Rate: 1.0 mV/ms max

Sample/Hold Offset Step: 3 mV max

Aperture Jitter: 0.5 ns

Extended Temperature Range: –55 C to +125 C

Internal Hold Capacitor

Internal Application Resistors

Available in Surface Mount

APPLICATIONS

Data Acquisition Systems

Data Distribution Systems

Analog Delay & Storage

Peak Amplitude Measurements

MIL-STD-883 Compliant Versions Available

12 V or

15 V Operation

0.01% max

The AD585 is available in three performance grades. The JP

grade is specified for the 0 C to +70 C commercial temperature

range and packaged in a 20-pin PLCC. The AQ grade is speci-

fied for the –25 C to +85 C industrial temperature range and is

packaged in a 14-pin cerdip. The SQ and SE grades are speci-

fied for the –55 C to +125 C military temperature range and

are packaged in a 14-pin cerdip and 20-pin LCC.

PRODUCT HIGHLIGHTS

1. The fast acquisition time (3 s) and low aperture jitter

2. The droop rate is only 1.0 mV/ms so that it may be used in

3. The low charge transfer of the analog switch keeps sample-to

4. The AD585 has internal pretrimmed application resistors for

5. The AD585 is complete with an internal hold capacitor for

6. The AD585 is recommended for use with 10- and 12-bit

7. The AD585 is available in versions compliant with MIL-STD-

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

acquisition systems.

slower high accuracy systems without the loss of accuracy.

hold offset below 3 mV with the on-chip 100 pF hold capaci-

tor, eliminating the trade-off between acquisition time and

S/H offset required with other SHAs.

applications versatility.

ease of use. Capacitance can be added externally to reduce

the droop rate when long hold times and high accuracy are

required.

successive-approximation A/D converters such as AD573,

AD574A, AD674A, AD7572 and AD7672.

883. Refer to the Analog Devices Military Products Databook

or current AD585/883B data sheet for detailed specifications.

(0.5 ns) make it the first choice for very high speed data

Sample-and-Hold Amplifier

DIP

FUNCTIONAL BLOCK DIAGRAM

High Speed, Precision

LCC/PLCC Package

AD585

Fax: 617/326-8703

Related parts for 5962-8754001CA

5962-8754001CA Summary of contents

Page 1

FEATURES 3.0 s Acquisition Time to 0.01% max Low Droop Rate: 1.0 mV/ms max Sample/Hold Offset Step max Aperture Jitter: 0.5 ns Extended Temperature Range: – +125 C Internal Hold Capacitor Internal Application Resistors 12 ...

Page 2

AD585–SPECIFICATIONS Model SAMPLE/HOLD CHARACTERISTICS Acquisition Time Step to 0.01 Step to 0.01% Aperture Time p-p Input, HOLD 0 V Aperture Jitter p-p Input, HOLD 0 V Settling Time p-p Input, ...

Page 3

ABSOLUTE MAXIMUM RATINGS Supplies (+V , – ...

Page 4

AD585 SAMPLED DATA SYSTEMS In sampled data systems there are a number of limiting factors in digitizing high frequency signals accurately. Figure 9 shows pictorially the sample-and-hold errors that are the limiting fac- tors. In the following discussions of error ...

Page 5

For the AD585 in particular it becomes: 0.3 pC S/H Offset (V ) 100 pF The addition of an external hold capacitor also affects the acqui- sition time of the AD585. The change in acquisition time with respect to the ...

Page 6

AD585 LOGIC INPUT The sample-and-hold logic control was designed for versatile logic interfacing. The HOLD and HOLD inputs may be used with both low and high level CMOS, TTL and ECL logic sys- tems. Logic threshold programmability was achieved by ...

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