AD9100AD Analog Devices Inc, AD9100AD Datasheet - Page 5

• Manufacturer Part Number: AD9100AD
• Manufacturer: Analog Devices Inc

Specifications of AD9100AD

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

REV. A
Acquisition Time is the amount of time it takes the AD9100 to
reacquire the analog input when switching from hold to track
mode. The interval starts at the 50% clock transition point and
ends when the input signal is reacquired to within a specified
error band at the hold capacitor.
Analog Delay is the time required for an analog input signal to
propagate from the device input to output.
Aperture Delay tells when the input signal is actually sampled.
It is the time difference between the analog propagation delay of
the front-end buffer and the control switch delay time. (The
time from the hold command transition to when the switch is
opened.) For the AD9100, this is a positive value which means
that the switch delay is longer than the analog delay.
Aperture Jitter is the random variation in the aperture delay.
This is measured in ps-rms and results in phase noise on the
held signal.
Droop Rate is the change in output voltage as a function of
time (dV/dt). It is measured at the AD9100 output with the
device in hold mode and the input held at a specified dc value,
the measurement starts immediately after the T/H switches from
track to hold. Feedthrough Rejection is the ratio of the input
signal to the output signal when in hold mode. This is a measure
of how well the switch isolates the input signal from feeding
through to the output.
Hold to Track Switch Delay is the time delay from the track
command to the point when the output starts to change and
acquire a new signal.
Pedestal Offset is the offset voltage step measured immediately
after the AD9100 is switched from track to hold with the input
held at zero volts. It manifests itself as an added offset during
the hold time.
Track to Hold Settling Time is the time necessary for the
track to hold switching transient to settle to within 1 mV of its
final value.
Track to Hold Switching Transient is the maximum peak
switch induced transient voltage which appears at the AD9100
output when it is switched from track to hold.
THEORY OF OPERATION
The AD9100 utilizes a new track and hold architecture.
Previous commercially available high speed track and holds used
an open loop input buffer, followed by a diode bridge, hold
capacitor, and output buffer (closed or open loop) with a FET
device connected to the hold capacitor. This architecture
required mixed device technology and, usually, hybrid
construction. The sampling rate of these hybrids has been
limited to 20 MSPS for 12-bit accuracy. Distortion generated in
the front-end amplifier/ bridge limited the dynamic range
performance to the “mid-70 dBfs” for analog input signals of
less than 10 MHz. Broadband and switch-generated noise
limited the SNR of previous track and holds to about 70 dB.
The AD9100 is a monolithic device using a high frequency
complementary bipolar process to achieve new levels of high
speed precision. Its patent pending architecture breaks from the
traditional architecture described above. (See the block diagram
–5–
on the first page.) The switching type bridge has been integrated
into the first stage closed loop input amplifier. This innovation
provides error (distortion) correction for both the switch and
amplifier, while still achieving slew rates representative of an
open-loop design. In addition, acquisition slew current for the
hold capacitor is higher than standard diode bridge and switch
configurations, removing a main contributor to the limits of
maximum sampling rate and input frequency.
Switching circuits in the device use current steering (versus
voltage switching) to provide improved isolation between the
switch and analog sections. This results in low aperture time
sensitivity to the analog input signal, and reduced power supply
and analog switching noise. Track to hold peak switching
transient is typically only 6 mV and settles to less than 1 mV in
7 ns. In addition, pedestal sensitivity to analog input voltage is
very low (0.6 mV/V) and being first order linear does not
significantly affect distortion.
The closed-loop output buffer includes zero voltage bias current
cancellation, which results in high-temperature droop rates
equivalent to those found in FET type inputs. The buffer also
provides first order quasistatic bias correction resulting in an
extremely high input resistance and very low droop sensitivity
vs. input voltage level (typically less than 1.5 mV/V– s.) This
closed-loop architecture inherently provides high speed loop
correction and results in low distortion under heavy loads.
The extremely fast time constant linearity (7 ns to 0.01% for a
2 V step) ensures that the output buffer does not limit the
AD9100 sampling rate or analog input frequency. (The
acquisition and settling time are primarily limited only by the
input amplifier and switch.) The output is transparent to the
overall AD9100 hold mode distortion levels for loads as low as
250 .
Full-scale track and acquisition slew rates achieved by the
AD9100 are 800 and 1000 V/ s, respectively. When combined
with excellent phase margin (typically 5% overshoot), wide
bandwidth, and dc gain accuracy, acquisition time to 0.01% is
only 16 ns. Though not production tested, settling to 14-bit
accuracy (–86 dB distortion @ 2.3 MHz) can be inferred to be
20 ns.
Acquisition Time
Acquisition time is the amount of time it takes the AD9100 to
reacquire the analog input when switching from hold to track
mode. The interval starts at the 50% clock transition point and
ends when the input signal is reacquired to within a specified
error band at the hold capacitor.
The hold to track switch delay (t
from this acquisition time because it is a charging time delay
that occurs when moving from hold to track; this is typically 4
to 6 ns and is the longest delay. Therefore, the track time
required for the AD9100 is the acquisition time minus the
aperture delay time. Note that the acquisition time is defined as
the settled voltage at the hold capacitor and does not include
the delay and settling time of the output buffer. The example
below illustrates why the output buffer amplifier does not
contribute to the overall AD9100 acquisition time.
DH
t) cannot be subtracted
AD9100