LT1719CS6#PBF Linear Technology, LT1719CS6#PBF Datasheet - Page 16

• Manufacturer Part Number: LT1719CS6#PBF
• Manufacturer: Linear Technology

Specifications of LT1719CS6#PBF

• Number Of Elements: 1
• Output Type: Open Collector
• Technology: BiCMOS
• Input Offset Voltage: 2.5@5VmV
• Input Bias Current (typ): 2500(Typ)nA
• Response Time: 1.3ns
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): ±3V
• Supply Current (max): 9mA
• Common Mode Rejection Ratio: 65dB
• Power Supply Rejection Ratio: 80dB
• Power Supply Requirement: Single/Dual
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 6V
• Dual Supply Voltage (min): ±1.35V
• Dual Supply Voltage (max): ±3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 6
• Package Type: TSOT-23
• Lead Free Status / RoHS Status: Compliant

LT1719
APPLICATIONS INFORMATION
Circuit Description
The block diagram of the LT1719 is shown in Figure 7.
The circuit topology consists of a differential input stage,
a gain stage with hysteresis and a complementary com-
mon-emitter output stage. All of the internal signal paths
utilize low voltage swings for high speed at low power.
The input stage topology maximizes the input dynamic
range available without requiring the power, complexity
and die area of two complete input stages such as are
found in rail-to-rail input comparators. With a single
2.7V supply, the LT1719 still has a respectable 1.6V of
input common mode range. The differential input volt-
age range is rail-to-rail, without the large input currents
found in competing devices. The input stage also features
phase reversal protection to prevent false outputs when
the inputs are driven below the –100mV common mode
voltage limit.
The internal hysteresis is imp lemented by positive, nonlin-
ear feedback around a second gain stage. Until this point,
the signal path has been entirely differential. The signal
path is then split into two drive signals for the upper and
16
+IN
–IN
+
–
V
V
A
CC
EE
V1
OR V
OR V
–
+
SHUTDOWN
+
∑
+
∑
NONLINEAR STAGE
Figure 7. LT1719 Block Diagram
+
–
BIAS CONTOL
A
V2
lower output transistors. The output transistors are con-
nected common emitter for rail-to-rail output operation.
The Schottky clamps limit the output voltages at about
300mV from the rail, not quite the 50mV or 15mV of Linear
Technology’s rail-to-rail amplifiers and other products. But
the output of a comparator is digital, and this output stage
can drive TTL or CMOS directly. It can also drive ECL, as
described earlier, or analog loads as demonstrated in the
applications to follow.
The bias conditions and signal swings in the output stage
are designed to turn their respective output transistors off
faster than on. This helps minimize the surge of current from
+ V
the frequency-dependent increase in power consumption.
The frequency dependence of the supply current is shown
in the Typical Performance Characteristics.
Speed Limits
The LT1719 comparator is intended for high speed ap-
plications, where it is important to understand a few
limitations. These limitations can roughly be divided into
S
/ V
+
to ground that occurs at transitions, to minimize
+
–
+
–
+V
GND OR V
OUT
S
OR V
1719 F07
+
–
1719fa