SGTL5000XNLA3R2 Freescale, SGTL5000XNLA3R2 Datasheet - Page 12

• Manufacturer Part Number: SGTL5000XNLA3R2
• Manufacturer: Freescale

Specifications of SGTL5000XNLA3R2

• Single Supply Voltage (typ): 1.8/2.5/3.3V
• Lead Free Status / RoHS Status: Compliant

POWER
the system designer to minimize power consumption and
maximize performance at the lowest cost.
External Power Supplies
and VDDIO. An optional third external power supply VDDD
may be provided externally to achieve lower power. A
description for the different power supplies is as follows:
• VDDA: This external power supply is used for the internal
• VDDIO: This external power supply controls the digital I/O
voltage, a single decoupling capacitor can be used to
minimize cost. This capacitor should be placed closest to
VDDA.
• VDDD: This is a digital power supply that is used for
Internal Power Supplies
VAG and charge pump.
• VAG is the internal voltage reference for the ADC and
• Chargepump: This power supply is used for internal
12
SGTL500
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
The SGTL5000 has a flexible power architecture to allow
The SGTL5000 requires 2 external power supplies: VDDA
analog circuitry including ADC, DAC, LINE inputs, MIC
inputs, headphone outputs and reference voltages. VDDA
supply ranges are shown in
decoupling cap should be used on VDDA, as shown in the
typical application diagrams in
levels as well as the output level of LINE outputs. VDDIO
supply ranges are shown in
decoupling cap should be used on VDDIO as shown in the
typical application diagrams in
Note that if VDDA and VDDIO are derived from the same
internal digital circuitry. For a low cost design, this supply
can be derived from an internal regulator and no external
components are required. If no external supply is applied
to VDDD, the internal regulator will automatically be used.
For lowest power, this supply can be driven at the lowest
specified voltage given in
supply is used for VDDD, a decoupling capacitor is
recommended. VDDD supply ranges are shown in
Maximum
system drives VDDD externally, an efficient switching
supply should be used or no system power savings will be
realized.
The SGTL5000 has two exposed internal power supplies,
DAC. After startup the voltage of VAG should be set to
VDDA/2 by writing CHIP_REF_CTRL->VAG_VAL. Refer
to programming
The VAG pin should have an external filter capacitor as
shown in the typical application diagram.
analog switches. If VDDA or VDDIO is greater than 2.7 V,
this supply is automatically driven from the highest of
Ratings, for when externally driven. If the
Chip Powerup and Supply
Maximum
Maximum
Maximum
Typical
Typical
Ratings. If an external
Ratings. A
Applications.
Ratings. A
Applications.
Configurations.
• LINE_OUT_VAG is the line output voltage reference. It
Power Schemes
the system designer to minimize power or maximize BOM
savings.
• For maximum cost savings, all supplies can be run at the
• Alternatively for minimum power, the analog and digital
• To save power, independent supplies are provided for line
• For best power, VDDA should be run at the lowest
RESET
SYS_MCLKs after all power rails have been brought up. After
this time communication can start. See
Characteristics.
CLOCKING
master clock input (SYS_MCLK). SYS_MCLK should be
synchronous to the sampling rate (Fs) of the I
Alternatively any clock between 8.0 and 27 Mhz can be
provided on SYS_MCLK and the SGTL5000 can use an
internal PLL to derive all internal and I
the system to use an available clock such as 12 MHz
(common USB clock) for SYS_MCLK to reduce overall
system costs.
Synchronous SYS_MCLK input
SYS_MCLK frequency and sampling frequency as shown in
Table 6. Using a synchronous SYS_MCLK allows for lower
power as the internal PLL is not used.
VDDIO and VDDA. If both VDDIO and VDDA are less than
3.1 V, then the user should turn on the charge pump
function to create the chargepump rail from VDDIO by
writing CHIP_ANA_POWER->
VDDC_CHRGPMP_POWERUP register. Refer to
programming
should be set to VDDIO/2 by writing
CHIP_LINE_OUT_CTRL->LO_VAGCNTRL.
The SGTL5000 supports a flexible architecture and allows
same voltage.
supplies can be run at minimum voltage while driving the
digital I/O voltage at the voltage needed by the system.
outputs and headphone outputs. This allows for 1VRMS
line outputs while using minimal headphone power.
possible voltage required for the maximum headphone
output level. For highest performance, VDDA should be
run at 3.3 V. For most applications a lower voltage can be
used for the best performance/power combination.
The SGTL5000 has an internal reset that is deasserted 8
Clocking for the SGTL5000 is provided by a system
The SGTL5000 supports various combinations of
Chip Powerup and Supply
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
S clocks. This allows
Dynamic Electrical
Configurations.
2
S port.